de2_default.hif

DE2开发版的默认程序

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sel0
sel1
sel2
sel3
sel4
sel5
sel6
result0
result1
result2
result3
result4
result5
result6
result7
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|mux_hkb:mux5
}
# end
# entity
mux_akb
# case_insensitive
# source_file
db|mux_akb.tdf
1152255088
6
# storage
db|DE2_Default.(14).cnf
db|DE2_Default.(14).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
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data66
data67
data68
data69
data70
data71
data72
data73
data74
sel0
sel1
sel2
sel3
sel4
sel5
sel6
result0
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|mux_akb:mux6
}
# end
# entity
I2C_AV_Config
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_AV_Config.v
1136525556
7
# storage
db|DE2_Default.(15).cnf
db|DE2_Default.(15).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
CLK_Freq
50000000
PARAMETER_DEC
DEF
I2C_Freq
20000
PARAMETER_DEC
DEF
LUT_SIZE
50
PARAMETER_DEC
DEF
SET_LIN_L
0
PARAMETER_DEC
DEF
SET_LIN_R
1
PARAMETER_DEC
DEF
SET_HEAD_L
2
PARAMETER_DEC
DEF
SET_HEAD_R
3
PARAMETER_DEC
DEF
A_PATH_CTRL
4
PARAMETER_DEC
DEF
D_PATH_CTRL
5
PARAMETER_DEC
DEF
POWER_ON
6
PARAMETER_DEC
DEF
SET_FORMAT
7
PARAMETER_DEC
DEF
SAMPLE_CTRL
8
PARAMETER_DEC
DEF
SET_ACTIVE
9
PARAMETER_DEC
DEF
SET_VIDEO
10
PARAMETER_DEC
DEF
}
# hierarchies {
I2C_AV_Config:u3
}
# end
# entity
I2C_Controller
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_Controller.v
1125366666
7
# storage
db|DE2_Default.(16).cnf
db|DE2_Default.(16).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
I2C_AV_Config:u3|I2C_Controller:u0
}
# end
# entity
AUDIO_DAC
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
AUDIO_DAC.v
1124062720
7
# storage
db|DE2_Default.(17).cnf
db|DE2_Default.(17).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
REF_CLK
18432000
PARAMETER_DEC
DEF
SAMPLE_RATE
48000
PARAMETER_DEC
DEF
DATA_WIDTH
16
PARAMETER_DEC
DEF
CHANNEL_NUM
2
PARAMETER_DEC
DEF
SIN_SAMPLE_DATA
48
PARAMETER_DEC
DEF
FLASH_DATA_NUM
1048576
PARAMETER_DEC
DEF
SDRAM_DATA_NUM
4194304
PARAMETER_DEC
DEF
SRAM_DATA_NUM
262144
PARAMETER_DEC
DEF
FLASH_ADDR_WIDTH
20
PARAMETER_DEC
DEF
SDRAM_ADDR_WIDTH
22
PARAMETER_DEC
DEF
SRAM_ADDR_WIDTH
18
PARAMETER_DEC
DEF
FLASH_DATA_WIDTH
8
PARAMETER_DEC
DEF
SDRAM_DATA_WIDTH
16
PARAMETER_DEC
DEF
SRAM_DATA_WIDTH
16
PARAMETER_DEC
DEF
SIN_SANPLE
0
PARAMETER_DEC
DEF
FLASH_DATA
1
PARAMETER_DEC
DEF
SDRAM_DATA
2
PARAMETER_DEC
DEF
SRAM_DATA
3
PARAMETER_DEC
DEF
}
# hierarchies {
AUDIO_DAC:u4
}
# end
# entity
LCD_TEST
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_TEST.v
1136525588
7
# storage
db|DE2_Default.(18).cnf
db|DE2_Default.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
LCD_INTIAL
0
PARAMETER_DEC
DEF
LCD_LINE1
5
PARAMETER_DEC
DEF
LCD_CH_LINE
21
PARAMETER_DEC
DEF
LCD_LINE2
22
PARAMETER_DEC
DEF
LUT_SIZE
38
PARAMETER_DEC
DEF
}
# hierarchies {
LCD_TEST:u5
}
# end
# entity
LCD_Controller
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_Controller.v
1124911122
7
# storage
db|DE2_Default.(19).cnf
db|DE2_Default.(19).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
CLK_Divide
16
PARAMETER_DEC
DEF
}
# hierarchies {
LCD_TEST:u5|LCD_Controller:u0
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|DE2_Default.(20).cnf
db|DE2_Default.(20).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_UNKNOWN
USR
WIDTHAD_A
6
PARAMETER_UNKNOWN
USR
NUMWORDS_A
64
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
DE2_Default0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ekk
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
clocken0
q_a0
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_ekk
# case_insensitive
# source_file
db|altsyncram_ekk.tdf
1152255122
6
# storage
db|DE2_Default.(21).cnf
db|DE2_Default.(21).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
clocken0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# memory_file {
DE2_Default0.rtl.mif
0
}
# end
# complete