de2_default.tan.rpt

DE2开发版的默认程序

+---------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+
; Worst-case tsu                                                ; N/A       ; None                             ; 3.426 ns                         ; KEY[0]                                   ; I2C_AV_Config:u3|altsyncram:rom_270_rtl_0|altsyncram_ekk:auto_generated|ram_block1a0~porta_address_reg5                                               ;                                                ; CLOCK_50                                       ; 0            ;
; Worst-case tco                                                ; N/A       ; None                             ; 14.604 ns                        ; AUDIO_DAC:u4|SEL_Cont[0]                 ; AUD_DACDAT                                                                                                                                            ; CLOCK_27                                       ;                                                ; 0            ;
; Worst-case tpd                                                ; N/A       ; None                             ; 10.547 ns                        ; SW[17]                                   ; AUD_DACDAT                                                                                                                                            ;                                                ;                                                ; 0            ;
; Worst-case th                                                 ; N/A       ; None                             ; -1.766 ns                        ; I2C_SDAT                                 ; I2C_AV_Config:u3|I2C_Controller:u0|ACK1                                                                                                               ;                                                ; CLOCK_50                                       ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0' ; 8.843 ns  ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; VGA_OSD_RAM:u2|oBlue[9]                  ; VGA_Controller:u1|Cur_Color_B[9]                                                                                                                      ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk2' ; 24.259 ns ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; VGA_Controller:u1|oAddress[14]           ; VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1' ; 52.837 ns ; 18.00 MHz ( period = 55.555 ns ) ; 367.92 MHz ( period = 2.718 ns ) ; AUDIO_DAC:u4|LRCK_1X_DIV[1]              ; AUDIO_DAC:u4|LRCK_1X                                                                                                                                  ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'CLOCK_50'                                       ; N/A       ; None                             ; 208.72 MHz ( period = 4.791 ns ) ; I2C_AV_Config:u3|I2C_Controller:u0|SD[3] ; I2C_AV_Config:u3|I2C_Controller:u0|SDO~reg0                                                                                                           ; CLOCK_50                                       ; CLOCK_50                                       ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'  ; 0.500 ns  ; 18.00 MHz ( period = 55.555 ns ) ; N/A                              ; AUDIO_DAC:u4|LRCK_1X                     ; AUDIO_DAC:u4|LRCK_1X                                                                                                                                  ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk2'  ; 0.626 ns  ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; VGA_OSD_RAM:u2|ADDR_d[2]                 ; VGA_OSD_RAM:u2|ADDR_dd[2]                                                                                                                             ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'  ; 0.637 ns  ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; VGA_Controller:u1|H_Cont[9]              ; VGA_Controller:u1|H_Cont[9]                                                                                                                           ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                  ;           ;                                  ;                                  ;                                          ;                                                                                                                                                       ;                                                ;                                                ; 0            ;
+---------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                  ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset     ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -2.324 ns  ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 18.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 2                     ; 3                   ; -2.324 ns  ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -12.246 ns ;              ;
; CLOCK_27                                       ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A        ;              ;