hdb3decoder.fit.qmsg

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 15 01:35:43 2005 " "Info: Processing started: Fri Jul 15 01:35:43 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off HDB3DECODER -c HDB3DECODER " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off HDB3DECODER -c HDB3DECODER" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "HDB3DECODER EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"HDB3DECODER\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 5 " "Info: No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "NRZ " "Info: Pin NRZ not assigned to an exact location on the device" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 8 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "NRZ" } } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { NRZ } "NODE_NAME" } "" } } { "F:/altera/hdb3decoder/HDB3DECODER.fld" "" { Floorplan "F:/altera/hdb3decoder/HDB3DECODER.fld" "" "" { NRZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { CLK } "NODE_NAME" } "" } } { "F:/altera/hdb3decoder/HDB3DECODER.fld" "" { Floorplan "F:/altera/hdb3decoder/HDB3DECODER.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { CLR } "NODE_NAME" } "" } } { "F:/altera/hdb3decoder/HDB3DECODER.fld" "" { Floorplan "F:/altera/hdb3decoder/HDB3DECODER.fld" "" "" { CLR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "NEG_IN " "Info: Pin NEG_IN not assigned to an exact location on the device" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 6 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "NEG_IN" } } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { NEG_IN } "NODE_NAME" } "" } } { "F:/altera/hdb3decoder/HDB3DECODER.fld" "" { Floorplan "F:/altera/hdb3decoder/HDB3DECODER.fld" "" "" { NEG_IN } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "POS_IN " "Info: Pin POS_IN not assigned to an exact location on the device" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 6 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "POS_IN" } } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { POS_IN } "NODE_NAME" } "" } } { "F:/altera/hdb3decoder/HDB3DECODER.fld" "" { Floorplan "F:/altera/hdb3decoder/HDB3DECODER.fld" "" "" { POS_IN } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 17 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 17" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLR Global clock in PIN 16 " "Info: Automatically promoted signal \"CLR\" to use Global clock in PIN 16" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.30 2 1 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.044 ns register register " "Info: Estimated most critical path is register to register delay of 2.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NEG_IN_TMP 1 REG LAB_X2_Y3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y3; Fanout = 6; REG Node = 'NEG_IN_TMP'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { NEG_IN_TMP } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 0.741 ns rtl~0 2 COMB LAB_X2_Y3 1 " "Info: 2: + IC(0.449 ns) + CELL(0.292 ns) = 0.741 ns; Loc. = LAB_X2_Y3; Fanout = 1; COMB Node = 'rtl~0'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "0.741 ns" { NEG_IN_TMP rtl~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 2.044 ns POS_FLAG 3 REG LAB_X2_Y3 2 " "Info: 3: + IC(0.436 ns) + CELL(0.867 ns) = 2.044 ns; Loc. = LAB_X2_Y3; Fanout = 2; REG Node = 'POS_FLAG'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "1.303 ns" { rtl~0 POS_FLAG } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.159 ns 56.70 % " "Info: Total cell delay = 1.159 ns ( 56.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.885 ns 43.30 % " "Info: Total interconnect delay = 0.885 ns ( 43.30 % )" {  } {  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.044 ns" { NEG_IN_TMP rtl~0 POS_FLAG } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 15 01:35:52 2005 " "Info: Processing ended: Fri Jul 15 01:35:52 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}