hdb3decoder.tan.qmsg

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 15 01:36:01 2005 " "Info: Processing started: Fri Jul 15 01:36:01 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off HDB3DECODER -c HDB3DECODER --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off HDB3DECODER -c HDB3DECODER --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } } { "f:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register NEG_IN_TMP register SEQUENCE\[3\] 164.31 MHz 6.086 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 164.31 MHz between source register \"NEG_IN_TMP\" and destination register \"SEQUENCE\[3\]\" (period= 6.086 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.782 ns + Longest register register " "Info: + Longest register to register delay is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NEG_IN_TMP 1 REG LC_X2_Y3_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { NEG_IN_TMP } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.442 ns) 0.969 ns SEQUENCE~611 2 COMB LC_X2_Y3_N5 1 " "Info: 2: + IC(0.527 ns) + CELL(0.442 ns) = 0.969 ns; Loc. = LC_X2_Y3_N5; Fanout = 1; COMB Node = 'SEQUENCE~611'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "0.969 ns" { NEG_IN_TMP SEQUENCE~611 } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.738 ns) 2.782 ns SEQUENCE\[3\] 3 REG LC_X1_Y3_N5 2 " "Info: 3: + IC(1.075 ns) + CELL(0.738 ns) = 2.782 ns; Loc. = LC_X1_Y3_N5; Fanout = 2; REG Node = 'SEQUENCE\[3\]'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "1.813 ns" { SEQUENCE~611 SEQUENCE[3] } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.180 ns 42.42 % " "Info: Total cell delay = 1.180 ns ( 42.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.602 ns 57.58 % " "Info: Total interconnect delay = 1.602 ns ( 57.58 % )" {  } {  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.782 ns" { NEG_IN_TMP SEQUENCE~611 SEQUENCE[3] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.782 ns" { NEG_IN_TMP SEQUENCE~611 SEQUENCE[3] } { 0.000ns 0.527ns 1.075ns } { 0.000ns 0.442ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { CLK } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns SEQUENCE\[3\] 2 REG LC_X1_Y3_N5 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y3_N5; Fanout = 2; REG Node = 'SEQUENCE\[3\]'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "1.261 ns" { CLK SEQUENCE[3] } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK SEQUENCE[3] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 SEQUENCE[3] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "" { CLK } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns NEG_IN_TMP 2 REG LC_X2_Y3_N4 6 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'" {  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "1.261 ns" { CLK NEG_IN_TMP } "NODE_NAME" } "" } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK NEG_IN_TMP } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 NEG_IN_TMP } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK SEQUENCE[3] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 SEQUENCE[3] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK NEG_IN_TMP } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 NEG_IN_TMP } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 48 -1 0 } } { "HDB3DECODER.vhd" "" { Text "F:/altera/hdb3decoder/HDB3DECODER.vhd" 18 -1 0 } }  } 0}  } { { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.782 ns" { NEG_IN_TMP SEQUENCE~611 SEQUENCE[3] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.782 ns" { NEG_IN_TMP SEQUENCE~611 SEQUENCE[3] } { 0.000ns 0.527ns 1.075ns } { 0.000ns 0.442ns 0.738ns } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK SEQUENCE[3] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 SEQUENCE[3] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" "" { Report "F:/altera/hdb3decoder/db/HDB3DECODER_cmp.qrpt" Compiler "HDB3DECODER" "UNKNOWN" "V1" "F:/altera/hdb3decoder/db/HDB3DECODER.quartus_db" { Floorplan "F:/altera/hdb3decoder/" "" "2.730 ns" { CLK NEG_IN_TMP } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 NEG_IN_TMP } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}