hdb3decoder.fit.eqn

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

--A1L7Q is NRZ~reg0 at LC_X1_Y3_N8
--operation mode is normal

A1L7Q_lut_out = GND;
A1L7Q = DFFEAS(A1L7Q_lut_out, GLOBAL(CLK), GLOBAL(CLR), , , SEQUENCE[3], , , VCC);


--SEQUENCE[3] is SEQUENCE[3] at LC_X1_Y3_N5
--operation mode is normal

SEQUENCE[3]_lut_out = SEQUENCE[2] & A1L71 # SEQUENCE[1] # SEQUENCE[0];
SEQUENCE[3] = DFFEAS(SEQUENCE[3]_lut_out, !GLOBAL(CLK), GLOBAL(CLR), , , , , , );


--SEQUENCE[2] is SEQUENCE[2] at LC_X1_Y3_N6
--operation mode is normal

SEQUENCE[2]_lut_out = GND;
SEQUENCE[2] = DFFEAS(SEQUENCE[2]_lut_out, !GLOBAL(CLK), GLOBAL(CLR), , , SEQUENCE[1], , , VCC);


--NEG_FLAG is NEG_FLAG at LC_X1_Y3_N9
--operation mode is normal

NEG_FLAG_lut_out = NEG_FLAG & NEG_IN_TMP # !POS_IN_TMP # !NEG_FLAG & NEG_IN_TMP & !POS_IN_TMP;
NEG_FLAG = DFFEAS(NEG_FLAG_lut_out, !GLOBAL(CLK), GLOBAL(CLR), , , , , , );


--POS_FLAG is POS_FLAG at LC_X2_Y3_N6
--operation mode is normal

POS_FLAG_lut_out = !NEG_IN_TMP & POS_IN_TMP;
POS_FLAG = DFFEAS(POS_FLAG_lut_out, !GLOBAL(CLK), GLOBAL(CLR), , A1L11, , , , );


--A1L71 is SEQUENCE~611 at LC_X2_Y3_N5
--operation mode is normal

POS_IN_TMP_qfbk = POS_IN_TMP;
A1L71 = NEG_IN_TMP & POS_IN_TMP_qfbk # !NEG_FLAG # !NEG_IN_TMP & !POS_IN_TMP_qfbk # !POS_FLAG;

--POS_IN_TMP is POS_IN_TMP at LC_X2_Y3_N5
--operation mode is normal

POS_IN_TMP = DFFEAS(A1L71, GLOBAL(CLK), GLOBAL(CLR), , , POS_IN, , , VCC);


--SEQUENCE[0] is SEQUENCE[0] at LC_X1_Y3_N4
--operation mode is normal

SEQUENCE[0]_lut_out = A1L81 # A1L91 & NEG_IN_TMP $ POS_IN_TMP;
SEQUENCE[0] = DFFEAS(SEQUENCE[0]_lut_out, !GLOBAL(CLK), GLOBAL(CLR), , , , , , );


--A1L11 is rtl~0 at LC_X2_Y3_N2
--operation mode is normal

A1L11 = NEG_IN_TMP $ POS_IN_TMP;


--A1L81 is SEQUENCE~613 at LC_X2_Y3_N4
--operation mode is normal

NEG_IN_TMP_qfbk = NEG_IN_TMP;
A1L81 = POS_IN_TMP & !POS_FLAG & !NEG_IN_TMP_qfbk # !POS_IN_TMP & NEG_IN_TMP_qfbk & !NEG_FLAG;

--NEG_IN_TMP is NEG_IN_TMP at LC_X2_Y3_N4
--operation mode is normal

NEG_IN_TMP = DFFEAS(A1L81, GLOBAL(CLK), GLOBAL(CLR), , , NEG_IN, , , VCC);


--A1L91 is SEQUENCE~614 at LC_X1_Y3_N2
--operation mode is normal

SEQUENCE[1]_qfbk = SEQUENCE[1];
A1L91 = SEQUENCE[0] # SEQUENCE[1]_qfbk # !SEQUENCE[3] & !SEQUENCE[2];

--SEQUENCE[1] is SEQUENCE[1] at LC_X1_Y3_N2
--operation mode is normal

SEQUENCE[1] = DFFEAS(A1L91, !GLOBAL(CLK), GLOBAL(CLR), , , SEQUENCE[0], , , VCC);


--CLK is CLK at PIN_17
--operation mode is input

CLK = INPUT();


--CLR is CLR at PIN_16
--operation mode is input

CLR = INPUT();


--NEG_IN is NEG_IN at PIN_33
--operation mode is input

NEG_IN = INPUT();


--POS_IN is POS_IN at PIN_32
--operation mode is input

POS_IN = INPUT();


--NRZ is NRZ at PIN_31
--operation mode is output

NRZ = OUTPUT(A1L7Q);