a8251.map.rpt

8251的完整的功能的实现,可以进行编译,综合.

    Info: Found entity 1: tx_fifo
Info: Found 2 design units, including 1 entities, in source file Tx_line_mux.vhd
    Info: Found design unit 1: tx_line_mux-rtl
    Info: Found entity 1: tx_line_mux
Info: Found 2 design units, including 1 entities, in source file Tx_par_gen.vhd
    Info: Found design unit 1: tx_par_gen-rtl
    Info: Found entity 1: tx_par_gen
Info: Found 2 design units, including 1 entities, in source file Tx_shift_reg.vhd
    Info: Found design unit 1: tx_shift_reg-rtl
    Info: Found entity 1: tx_shift_reg
Info: Found 2 design units, including 1 entities, in source file Tx_state_mach.vhd
    Info: Found design unit 1: tx_state_mach-rtl
    Info: Found entity 1: tx_state_mach
Info: Found 2 design units, including 1 entities, in source file Tx_status_reg.vhd
    Info: Found design unit 1: tx_status_reg-rtl
    Info: Found entity 1: tx_status_reg
Info: Found 2 design units, including 1 entities, in source file wr_ext.vhd
    Info: Found design unit 1: Wr_Ext-rtl
    Info: Found entity 1: Wr_Ext
Info: Found 2 design units, including 1 entities, in source file wr_sync.vhd
    Info: Found design unit 1: WriteSync-rtl
    Info: Found entity 1: WriteSync
Info: Found 2 design units, including 1 entities, in source file A8251.vhd
    Info: Found design unit 1: a8251-struct
    Info: Found entity 1: a8251
Info: Elaborating entity "A8251" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at A8251.vhd(91): object "tran_en" declared but not used
Info: (10035) Verilog HDL or VHDL information at A8251.vhd(105): object "tx_fifo_din" declared but not used
Info: (10035) Verilog HDL or VHDL information at A8251.vhd(114): object "cmnd_out" declared but not used
Info: Elaborating entity "dout_mux" for hierarchy "dout_mux:i_dout_mux"
Info: Elaborating entity "DataLatch" for hierarchy "DataLatch:i_DataSync"
Warning: VHDL Process Statement warning at data_latch.vhd(59): signal or variable "LatchedData" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "LatchedData" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "AddrLatch" for hierarchy "AddrLatch:i_AddrSync"
Warning: VHDL Process Statement warning at addr_latch.vhd(63): signal or variable "LatchedAddr" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "LatchedAddr" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "Wr_Ext" for hierarchy "Wr_Ext:i_Wr_Ext"
Info: Elaborating entity "proc" for hierarchy "proc:i_procintf"
Info: (10035) Verilog HDL or VHDL information at Proc.vhd(88): object "int_rxir" declared but not used
Info: Elaborating entity "proc_cmd_reg" for hierarchy "proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg"
Info: Elaborating entity "proc_mode_reg" for hierarchy "proc:i_procintf|proc_mode_reg:I_proc_mode_reg"
Info: Elaborating entity "proc_dec" for hierarchy "proc:i_procintf|proc_dec:I_proc_dec"
Info: Elaborating entity "proc_sm" for hierarchy "proc:i_procintf|proc_sm:I_proc_sm"
Info: Elaborating entity "proc_sync_reg" for hierarchy "proc:i_procintf|proc_sync_reg:I_proc_sync_reg1"
Info: Elaborating entity "rx" for hierarchy "rx:i_rx"
Info: Elaborating entity "rx_ready_reg" for hierarchy "rx:i_rx|rx_ready_reg:I_rx_ready_reg"
Info: Elaborating entity "rx_cntrl" for hierarchy "rx:i_rx|rx_cntrl:i_rx_cntrl"
Info: Elaborating entity "rx_cntrl_sm" for hierarchy "rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm"
Info: Elaborating entity "rx_cntrl_cnt" for hierarchy "rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_cnt:i_rx_cntrl_cnt"
Info: Elaborating entity "rx_det_cntrl" for hierarchy "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl"
Info: Elaborating entity "rx_sync_comp" for hierarchy "rx:i_rx|rx_sync_comp:i_rx_sync_comp"
Info: Elaborating entity "rx_shift_reg" for hierarchy "rx:i_rx|rx_shift_reg:i_rx_shift_reg"
Info: Elaborating entity "rx_data_reg" for hierarchy "rx:i_rx|rx_data_reg:i_rx_data_reg"
Info: Elaborating entity "rx_data_cnt" for hierarchy "rx:i_rx|rx_data_cnt:i_rx_data_cnt"
Info: Elaborating entity "rx_par_tree" for hierarchy "rx:i_rx|rx_par_tree:i_rx_par_tree"
Info: Elaborating entity "rx_error_reg" for hierarchy "rx:i_rx|rx_error_reg:i1_rx_error_reg"
Info: Elaborating entity "rx_break_cnt" for hierarchy "rx:i_rx|rx_break_cnt:i_rx_break_cnt"
Info: VHDL Case Statement information at Rx_break_cnt.vhd(174): OTHERS choice is never selected
Info: VHDL Case Statement information at Rx_break_cnt.vhd(233): OTHERS choice is never selected
Info: VHDL Case Statement information at Rx_break_cnt.vhd(292): OTHERS choice is never selected
Info: VHDL Case Statement information at Rx_break_cnt.vhd(298): OTHERS choice is never selected
Info: VHDL Case Statement information at Rx_break_cnt.vhd(339): OTHERS choice is never selected
Info: Elaborating entity "rx_sync_stat" for hierarchy "rx:i_rx|rx_sync_stat:i_rx_sync_stat"
Info: Elaborating entity "tx" for hierarchy "tx:i_tx"
Info: (10035) Verilog HDL or VHDL information at Tx.vhd(73): object "break" declared but not used
Info: (10035) Verilog HDL or VHDL information at Tx.vhd(74): object "stop" declared but not used
Info: (10035) Verilog HDL or VHDL information at Tx.vhd(75): object "start" declared but not used
Info: (10035) Verilog HDL or VHDL information at Tx.vhd(77): object "di" declared but not used
Info: Elaborating entity "tx_cntrl" for hierarchy "tx:i_tx|tx_cntrl:i_tx_cntrl"
Info: Elaborating entity "tx_state_mach" for hierarchy "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach"
Info: Elaborating entity "tx_data_cnt" for hierarchy "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt"
Info: Elaborating entity "tx_clk_div" for hierarchy "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div"
Info: Elaborating entity "tx_data_mux" for hierarchy "tx:i_tx|tx_data_mux:i_tx_data_mux"
Info: Elaborating entity "tx_par_gen" for hierarchy "tx:i_tx|tx_par_gen:i_tx_par_gen"
Info: Elaborating entity "tx_shift_reg" for hierarchy "tx:i_tx|tx_shift_reg:i_tx_shift_reg"
Info: Elaborating entity "tx_line_mux" for hierarchy "tx:i_tx|tx_line_mux:i_tx_line_mux"
Info: Elaborating entity "tx_fifo" for hierarchy "tx_fifo:i_tx_fifo"
Info: State machine "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state" contains 8 states and 0 state bits
Info: State machine "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state" contains 5 states and 0 state bits
Info: State machine "|a8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state" contains 19 states and 0 state bits
Info: State machine "|a8251|proc:i_procintf|proc_sm:I_proc_sm|state" contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state"
Info: Encoding result for state machine "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop2"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop1"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.parity"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.data"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync2"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync1"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.start"
        Info: Encoded state bit "tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.init"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.init" uses code string "00000000"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.start" uses code string "00000011"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync1" uses code string "00000101"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync2" uses code string "00001001"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.data" uses code string "00010001"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.parity" uses code string "00100001"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop1" uses code string "01000001"
    Info: State "|a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop2" uses code string "10000001"
Info: Selected Auto state machine encoding method for state machine "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state"
Info: Encoding result for state machine "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.synced2"
        Info: Encoded state bit "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.synced1"
        Info: Encoded state bit "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.find_sync2"
        Info: Encoded state bit "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.hunt_sync"
        Info: Encoded state bit "rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.idle"
    Info: State "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.idle" uses code string "00000"
    Info: State "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.hunt_sync" uses code string "00011"
    Info: State "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.find_sync2" uses code string "00101"
    Info: State "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.synced1" uses code string "01001"
    Info: State "|a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state.synced2" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|a8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state"
Info: Encoding result for state machine "|a8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state"
    Info: Completed encoding using 19 state bits
        Info: Encoded state bit "rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state.db1_stop2"
        Info: Encoded state bit "rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state.db1_stop1"
        Info: Encoded state bit "rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state.db1_parity"
        Info