a8251.fit.qmsg

8251的完整的功能的实现,可以进行编译,综合.

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rx:i_rx\|rx_error_reg:i1_rx_error_reg\|sync_proc~0 Global clock " "Info: Automatically promoted signal \"rx:i_rx\|rx_error_reg:i1_rx_error_reg\|sync_proc~0\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rx:i_rx\|rx_error_reg:i1_rx_error_reg\|sync_proc~0" } } } } { "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" "" { Report "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" Compiler "A8251" "UNKNOWN" "V1" "E:/UNZIPPED/8251_OSED/db/A8251.quartus_db" { Floorplan "E:/UNZIPPED/8251_OSED/" "" "" { rx:i_rx|rx_error_reg:i1_rx_error_reg|sync_proc~0 } "NODE_NAME" } "" } } { "E:/UNZIPPED/8251_OSED/A8251.fld" "" { Floorplan "E:/UNZIPPED/8251_OSED/A8251.fld" "" "" { rx:i_rx|rx_error_reg:i1_rx_error_reg|sync_proc~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|rxsync_proc2~0 Global clock " "Info: Automatically promoted signal \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|rxsync_proc2~0\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|rxsync_proc2~0" } } } } { "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" "" { Report "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" Compiler "A8251" "UNKNOWN" "V1" "E:/UNZIPPED/8251_OSED/db/A8251.quartus_db" { Floorplan "E:/UNZIPPED/8251_OSED/" "" "" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|rxsync_proc2~0 } "NODE_NAME" } "" } } { "E:/UNZIPPED/8251_OSED/A8251.fld" "" { Floorplan "E:/UNZIPPED/8251_OSED/A8251.fld" "" "" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|rxsync_proc2~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}