a8251.map.eqn

来自「8251的完整的功能的实现,可以进行编译,综合.」· EQN 代码 · 共 2,099 行 · 第 1/5 页

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--LB1_state.parity is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.parity
--operation mode is normal

LB1_state.parity_lut_out = JB1L91 & (LB1L92) # !JB1L91 & LB1_state.parity;
LB1_state.parity = DFFEAS(LB1_state.parity_lut_out, !nTxC, reset, , , LB1L03, , !K1_tx_resetn, V1L7);


--GB1_parity is tx:i_tx|tx_par_gen:i_tx_par_gen|parity
--operation mode is normal

GB1_parity_lut_out = EB1L71 $ EB1L51 $ GB1L1 $ !GB1L2;
GB1_parity = DFFEAS(GB1_parity_lut_out, !nTxC, reset, , LB1L74, , , , );


--M1_int_dout[1] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[1]
--operation mode is normal

M1_int_dout[1]_lut_out = A1L54;
M1_int_dout[1] = DFFEAS(M1_int_dout[1]_lut_out, clk, reset, , A1L64, , , , );


--M1_int_dout[0] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[0]
--operation mode is normal

M1_int_dout[0]_lut_out = A1L74;
M1_int_dout[0] = DFFEAS(M1_int_dout[0]_lut_out, clk, reset, , A1L64, , , , );


--V1L7 is rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|next_state.hunt_sync~141
--operation mode is normal

V1L7 = !M1_int_dout[1] & !M1_int_dout[0];


--LB1_state.init is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.init
--operation mode is normal

LB1_state.init_lut_out = !LB1L51 & (V1L7 # !LB1L61 & LB1L01);
LB1_state.init = DFFEAS(LB1_state.init_lut_out, !nTxC, reset, , , , , , );


--LB1_state.start is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.start
--operation mode is normal

LB1_state.start_lut_out = LB1L9 & (LB1L71 # !LB1L33 # !LB1L52);
LB1_state.start = DFFEAS(LB1_state.start_lut_out, !nTxC, reset, , , , , , );


--LB1_state.stop2 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop2
--operation mode is normal

LB1_state.stop2_lut_out = LB1L9 & (LB1L91 # LB1_state.stop2 & !LB1L66);
LB1_state.stop2 = DFFEAS(LB1_state.stop2_lut_out, !nTxC, reset, , , , , , );


--LB1_state.stop1 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.stop1
--operation mode is normal

LB1_state.stop1_lut_out = LB1L9 & (JB1L91 & LB1L81 # !JB1L91 & (LB1_state.stop1));
LB1_state.stop1 = DFFEAS(LB1_state.stop1_lut_out, !nTxC, reset, , , , , , );


--LB1L82 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|Select~1341
--operation mode is normal

LB1L82 = LB1_state.init & !LB1_state.start & !LB1_state.stop2 & !LB1_state.stop1;


--K1_tx_resetn is proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|tx_resetn
--operation mode is normal

K1_tx_resetn_lut_out = VCC;
K1_tx_resetn = DFFEAS(K1_tx_resetn_lut_out, nTxC, !K1L71, , , , , , );


--FB1L1 is tx:i_tx|tx_line_mux:i_tx_line_mux|txdata~813
--operation mode is normal

FB1L1 = LB1_state.parity & GB1_parity & !FB1L5 # !K1_tx_resetn;


--LB1_state.data is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.data
--operation mode is normal

LB1_state.data_lut_out = M1_int_dout[1] & (LB1L34) # !M1_int_dout[1] & (M1_int_dout[0] & (LB1L34) # !M1_int_dout[0] & LB1L14);
LB1_state.data = DFFEAS(LB1_state.data_lut_out, !nTxC, reset, , , , , !K1_tx_resetn, );


--FB1L2 is tx:i_tx|tx_line_mux:i_tx_line_mux|txdata~814
--operation mode is normal

FB1L2 = LB1_state.data & GB1_parity;


--HB1_data_int[0] is tx:i_tx|tx_shift_reg:i_tx_shift_reg|data_int[0]
--operation mode is normal

HB1_data_int[0]_lut_out = LB1L05 & (K1_tx_resetn & EB1L2 # !K1_tx_resetn & (HB1_data_int[1])) # !LB1L05 & (HB1_data_int[1]);
HB1_data_int[0] = DFFEAS(HB1_data_int[0]_lut_out, !nTxC, reset, , A1L44, , , !K1_tx_resetn, );


--FB1L3 is tx:i_tx|tx_line_mux:i_tx_line_mux|txdata~815
--operation mode is normal

FB1L3 = FB1L5 # LB1_state.start & FB1L2 # !LB1_state.start & (FB1L6);


--K1_cmd_reg[3] is proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[3]
--operation mode is normal

K1_cmd_reg[3]_lut_out = C1_LatchedData[3]$latch & !K1_hunt & (K1_int_proc_resetn1 # !K1_cmd_reg[6]);
K1_cmd_reg[3] = DFFEAS(K1_cmd_reg[3]_lut_out, clk, reset, , A1L34, , , , );


--FB1L4 is tx:i_tx|tx_line_mux:i_tx_line_mux|txdata~816
--operation mode is normal

FB1L4 = !K1_cmd_reg[3] & (FB1L1 # FB1L3 & !LB1_state.parity);


--K1_cmd_reg[0] is proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]
--operation mode is normal

K1_cmd_reg[0]_lut_out = C1_LatchedData[0]$latch & !K1_hunt & (K1_int_proc_resetn1 # !K1_cmd_reg[6]);
K1_cmd_reg[0] = DFFEAS(K1_cmd_reg[0]_lut_out, clk, reset, , A1L34, , , , );


--H1_ef_n is tx_fifo:i_tx_fifo|ef_n
--operation mode is normal

H1_ef_n_lut_out = VCC;
H1_ef_n = DFFEAS(H1_ef_n_lut_out, L1L7, !H1L4, , , , , , );


--A1L82 is int_txrdy~11
--operation mode is normal

A1L82 = K1_cmd_reg[0] & (!H1_ef_n & !nCTS);


--A1L92 is int_txrdy~12
--operation mode is normal

A1L92 = K1_cmd_reg[0] & (!nCTS);


--LB1_state.sync1 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync1
--operation mode is normal

LB1_state.sync1_lut_out = LB1L02 & (LB1L22 # LB1_state.sync1 & KB1L9);
LB1_state.sync1 = DFFEAS(LB1_state.sync1_lut_out, !nTxC, reset, , , , , , );


--LB1_state.sync2 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state.sync2
--operation mode is normal

LB1_state.sync2_lut_out = LB1L02 & (LB1L32 # LB1L23 & LB1L42);
LB1_state.sync2 = DFFEAS(LB1_state.sync2_lut_out, !nTxC, reset, , , , , , );


--LB1L31 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|next_state.init~546
--operation mode is normal

LB1L31 = !LB1_state.data & !LB1_state.sync1 & !LB1_state.sync2;


--M1_int_dout[4] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[4]
--operation mode is normal

M1_int_dout[4]_lut_out = A1L95;
M1_int_dout[4] = DFFEAS(M1_int_dout[4]_lut_out, clk, reset, , A1L64, , , , );


--KB1_bit_cnt[2] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt|bit_cnt[2]
--operation mode is normal

KB1_bit_cnt[2]_lut_out = !KB1L8 & (KB1_bit_cnt[2] $ (KB1_bit_cnt[1] & KB1L1));
KB1_bit_cnt[2] = DFFEAS(KB1_bit_cnt[2]_lut_out, !nTxC, reset, , , , , , );


--KB1_bit_cnt[1] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt|bit_cnt[1]
--operation mode is normal

KB1_bit_cnt[1]_lut_out = !KB1L8 & (KB1_bit_cnt[1] $ KB1L1);
KB1_bit_cnt[1] = DFFEAS(KB1_bit_cnt[1]_lut_out, !nTxC, reset, , , , , , );


--KB1_bit_cnt[0] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt|bit_cnt[0]
--operation mode is normal

KB1_bit_cnt[0]_lut_out = !KB1L8 & (KB1_bit_cnt[0] $ (K1_tx_resetn & LB1L44));
KB1_bit_cnt[0] = DFFEAS(KB1_bit_cnt[0]_lut_out, !nTxC, reset, , , , , , );


--M1_int_dout[2] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[2]
--operation mode is normal

M1_int_dout[2]_lut_out = A1L84;
M1_int_dout[2] = DFFEAS(M1_int_dout[2]_lut_out, clk, reset, , A1L64, , , , );


--M1_int_dout[3] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[3]
--operation mode is normal

M1_int_dout[3]_lut_out = A1L24;
M1_int_dout[3] = DFFEAS(M1_int_dout[3]_lut_out, clk, reset, , A1L64, , , , );


--LB1L1 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|data_cnt_clr~110
--operation mode is normal

LB1L1 = KB1_bit_cnt[1] & M1_int_dout[3] & (KB1_bit_cnt[0] $ !M1_int_dout[2]) # !KB1_bit_cnt[1] & !M1_int_dout[3] & (KB1_bit_cnt[0] $ !M1_int_dout[2]);


--KB1L9 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt|data_tc~40
--operation mode is normal

KB1L9 = !LB1L1 # !KB1_bit_cnt[2] # !reset;


--A1L22 is int_txempty~647
--operation mode is normal

A1L22 = !KB1L9 & (M1_int_dout[4] # !nCTS & K1_cmd_reg[0]);


--A1L32 is int_txempty~648
--operation mode is normal

A1L32 = LB1_state.parity & (!LB1L31 & !A1L22 # !A1L92) # !LB1_state.parity & (!LB1L31 & !A1L22);


--JB1_int_dout[1] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[1]
--operation mode is arithmetic

JB1_int_dout[1]_carry_eqn = JB1L3;
JB1_int_dout[1]_lut_out = JB1_int_dout[1] $ (JB1_int_dout[1]_carry_eqn);
JB1_int_dout[1] = DFFEAS(JB1_int_dout[1]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L5 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[1]~50
--operation mode is arithmetic

JB1L5 = CARRY(!JB1L3 # !JB1_int_dout[1]);


--JB1_int_dout[4] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[4]
--operation mode is arithmetic

JB1_int_dout[4]_carry_eqn = JB1L9;
JB1_int_dout[4]_lut_out = JB1_int_dout[4] $ (!JB1_int_dout[4]_carry_eqn);
JB1_int_dout[4] = DFFEAS(JB1_int_dout[4]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L11 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[4]~54
--operation mode is arithmetic

JB1L11 = CARRY(JB1_int_dout[4] & (!JB1L9));


--JB1L51 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|reduce_nor~64
--operation mode is normal

JB1L51 = JB1_int_dout[1] & M1_int_dout[1] & (M1_int_dout[0] $ !JB1_int_dout[4]) # !JB1_int_dout[1] & !M1_int_dout[1] & (!JB1_int_dout[4]);


--JB1_int_dout[2] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[2]
--operation mode is arithmetic

JB1_int_dout[2]_carry_eqn = JB1L5;
JB1_int_dout[2]_lut_out = JB1_int_dout[2] $ (!JB1_int_dout[2]_carry_eqn);
JB1_int_dout[2] = DFFEAS(JB1_int_dout[2]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L7 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[2]~58
--operation mode is arithmetic

JB1L7 = CARRY(JB1_int_dout[2] & (!JB1L5));


--JB1_int_dout[0] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[0]
--operation mode is arithmetic

JB1_int_dout[0]_lut_out = LB1L21 $ JB1_int_dout[0];
JB1_int_dout[0] = DFFEAS(JB1_int_dout[0]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L3 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[0]~62
--operation mode is arithmetic

JB1L3 = CARRY(LB1L21 & JB1_int_dout[0]);


--JB1_int_dout[6] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[6]
--operation mode is normal

JB1_int_dout[6]_carry_eqn = JB1L31;
JB1_int_dout[6]_lut_out = JB1_int_dout[6] $ (!JB1_int_dout[6]_carry_eqn);
JB1_int_dout[6] = DFFEAS(JB1_int_dout[6]_lut_out, !nTxC, reset, , , , , LB1L8, );


--JB1L61 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|reduce_nor~65
--operation mode is normal

JB1L61 = !JB1_int_dout[6] & (JB1_int_dout[2] & JB1_int_dout[0] & M1_int_dout[1] # !JB1_int_dout[2] & !JB1_int_dout[0] & !M1_int_dout[1]);


--JB1_int_dout[3] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[3]
--operation mode is arithmetic

JB1_int_dout[3]_carry_eqn = JB1L7;
JB1_int_dout[3]_lut_out = JB1_int_dout[3] $ (JB1_int_dout[3]_carry_eqn);
JB1_int_dout[3] = DFFEAS(JB1_int_dout[3]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L9 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[3]~70
--operation mode is arithmetic

JB1L9 = CARRY(!JB1L7 # !JB1_int_dout[3]);


--JB1_int_dout[5] is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[5]
--operation mode is arithmetic

JB1_int_dout[5]_carry_eqn = JB1L11;
JB1_int_dout[5]_lut_out = JB1_int_dout[5] $ (JB1_int_dout[5]_carry_eqn);
JB1_int_dout[5] = DFFEAS(JB1_int_dout[5]_lut_out, !nTxC, reset, , , , , LB1L8, );

--JB1L31 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|int_dout[5]~74
--operation mode is arithmetic

JB1L31 = CARRY(!JB1L11 # !JB1_int_dout[5]);


--JB1L71 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|reduce_nor~66
--operation mode is normal

JB1L71 = JB1_int_dout[3] & M1_int_dout[1] & (M1_int_dout[0] $ !JB1_int_dout[5]) # !JB1_int_dout[3] & !M1_int_dout[1] & (!JB1_int_dout[5]);


--JB1L81 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div|tc~135
--operation mode is normal

JB1L81 = JB1L51 & JB1L61 & JB1L71 # !M1_int_dout[1];


--LB1L9 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|div_cnt_en~173
--operation mode is normal

LB1L9 = K1_tx_resetn & (M1_int_dout[1] # M1_int_dout[0]);


--M1_int_dout[7] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[7]
--operation mode is normal

M1_int_dout[7]_lut_out = A1L05;
M1_int_dout[7] = DFFEAS(M1_int_dout[7]_lut_out, clk, reset, , A1L64, , , , );


--A1L42 is int_txempty~649
--operation mode is normal

A1L42 = LB1_state.stop1 & JB1L81 & LB1L9 & !M1_int_dout[7];


--M1_int_dout[6] is proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[6]
--operation mode is normal

M1_int_dout[6]_lut_out = A1L94;
M1_int_dout[6] = DFFEAS(M1_int_dout[6]_lut_out, clk, reset, , A1L64, , , , );


--LB1L36 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|statetran~298
--operation mode is normal

LB1L36 = JB1L51 & JB1L61 & JB1L71 & M1_int_dout[6];


--LB1L46 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|statetran~299
--operation mode is normal

LB1L46 = JB1_int_dout[5] # M1_int_dout[6] # M1_int_dout[0] $ JB1_int_dout[3];


--LB1L56 is tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|statetran~300
--operation mode is normal

LB1L56 = JB1L51 & JB1L61 & !LB1L46 # !M1_int_dout[1];


--A1L52 is int_txempty~650
--operation mode is normal

A1L52 = LB1_state.stop2 & LB1L9 & (LB1L36 # LB1L56);


--A1L62 is int_txempty~651
--operation mode is normal

A1L62 = V1L7 & A1L32 # !V1L7 & (A1L42 # A1L52);


--A1L72 is int_txempty~652
--operation mode is normal

A1L72 = H1_ef_n # K1_tx_resetn & A1L62;


--X1_rxrdy is rx:i_rx|rx_ready_reg:I_rx_ready_reg|rxrdy
--operation mode is normal

X1_rxrdy_lut_out = K1_rx_resetn;