hub.c

RDC R2886 Ethernet hub功能 源码,paradigm c++上运行测试

      desc_ptr->vndesc_ptr = (desc_ptr + 1);
		desc_ptr->status = 0x8000;
      r_desc_addr += RDC_DESC_SIZE;
      r_buf_addr += BUF_SIZE;
      desc_ptr += 1;
		buf_ptr = (buf_ptr + BUF_SIZE);
   }
   (desc_ptr - 1)->ndesc_ptr = mac_ipr->rxd_raddr;
   (desc_ptr - 1)->vndesc_ptr = mac_ipr->rx_insert_ptr;
}

/* Initilize system
	Disable Watch-dog timer, Enable RCU,
	Re-fresh count, PIO, Register interrupt handler	*/
void init_system(void)
{
   outport(0xffa0, 0xC033);		/* UCS */
   outport(0xffa2, 0x7000);		/* LCS */
   outport(0xffa8, 0x8002);		/* PCS & MCS auxiliary */
   outport(0xffa4, 0x0002);		/* 08/06 Sten */
 	outport(0xfef2, SDRAM_MODE_D);	/* SDRAM mode setting */
 	outport(0xfef4, SDRAM_CTRL_D);	/* SDRAM control register */
 	outport(0xfef6, SDRAM_TIMING_D);	/* SDRAM timing register */
 	outport(0xfffa, SDRAM_DELAYL_D);	/* SDRAM delay line register */
 	outport(0xffe2, REFRESH_COUNT_D)	;/* Clock pre-scaler for re-fresh */
 	outport(0xffe4, 0x8000);		/* Enable RCU Register */
 	outport(0xffe6, 0x3333);		/* Watch-dog Timer write sequence */
 	outport(0xffe6, 0xcccc);		/* Watch-dog Timer write sequence */
 	outport(0xffe6, 0x0000);		/* Disable Watch-dog timer */
   outport(0xffea, 0x0100);

 	/* PIO mode */
 	outport(0xff76, 0x0000);
 	outport(0xff70, 0x0000);
 	/* PIO direction */
 	outport(0xff78, 0x7800);		/* PIO 27,28,29,30 input */
 	outport(0xff72, 0x0000);
   outport(0xff7e, 0x0000);
   outport(0xff6c, 0x0000);

   /* Register Interrupt 4 handler */
   setvect(INT4_TYPE, int4_handler);
   
       /* Register UART0 Interrupt handler */
   setvect(UART0_TYPE, uart0_handler);

   /* Register UART1 Interrupt handler */
   setvect(UART1_TYPE, uart1_handler);
}

   

/* Find PHY chip address
	Search from 0x00 to 0x1F				*/
int find_phy_addr(MAC_STRU * mac_ipr)
{
	uint16 tmpv;

   for (mac_ipr->phy_addr = 0; mac_ipr->phy_addr < 0x2000; mac_ipr->phy_addr += 0x0100) {
   	tmpv = mii_read(mac_ipr, 2);
      if ((tmpv != 0) && (tmpv != 0xffff)) break;
   }

   return mac_ipr->phy_addr >= 0x2000 ? 1:0;
}

/* Write PHY register by MII interface */
int mii_write(MAC_STRU *mac_ipr, int offset, int wdata)
{
	int tmpv;
	int io_base = mac_ipr->io_base;

   outport(io_base + IO_MMWD, wdata);
   outport(io_base + IO_MMDIO, offset + mac_ipr->phy_addr + MIIWR);

   /* Wait command activate */
   while(!(inport(io_base + IO_MMDIO) & MIIWR));

   /* Wait command finish */
   do{
   	tmpv = inport(io_base + IO_MMDIO);
   } while(tmpv & MIIWR);

	return 0;
}

/* Read PHY register by MII interface */
int mii_read(MAC_STRU *mac_ipr, int offset)
{
	int tmpv;
	int io_base = mac_ipr->io_base;

   outport(io_base + IO_MMDIO, offset + mac_ipr->phy_addr + MIIRD);

   /* Wait command activate */
   while(!(inport(io_base + IO_MMDIO) & MIIRD));

   /* Wait command finish */
   do{
   	tmpv = inport(io_base + IO_MMDIO);
   } while(tmpv & MIIRD);

   return inport(io_base + IO_MMRD);
}

/* Send packet */
int send_pkt(MAC_STRU *mac_ipr, char * buf_ptr, int len)
{
	int	io_base = mac_ipr->io_base;
   RDC_DESCRIPTOR *txd_ptr;

   if (!mac_ipr->TxFreeDesc) return 1;

   disable();		/* Disable interrupt */
   txd_ptr = mac_ipr->tx_insert_ptr;
	txd_ptr->len = len;
   txd_ptr->status = 0x8000;
   mac_ipr->TxFreeDesc--;
   outport(io_base + IO_MTPR, 1);
   mac_ipr->tx_insert_ptr = txd_ptr->vndesc_ptr;
   enable();		/* Enable interrupt */

   return 0;
}

/* Send complete check */
void send_complete(MAC_STRU *mac_ipr)
{
   RDC_DESCRIPTOR *txd_ptr = mac_ipr->tx_remove_ptr;

   while(mac_ipr->TxFreeDesc < DESC_COUNT) {
   	if (txd_ptr->status & 0x8000) break;
      txd_ptr = txd_ptr->vndesc_ptr;
      mac_ipr->TxFreeDesc++;
      mac_ipr->TxSuccCounter++;
	}
   mac_ipr->tx_remove_ptr = txd_ptr;
}

/* Receive packet */
void receive_pkt(MAC_STRU *mac_ipr)
{
   RDC_DESCRIPTOR *rxd_ptr = mac_ipr->rx_remove_ptr;

   while(mac_ipr->RxFreeDesc) {
   	if (rxd_ptr->status & 0x8000) break;
		mac_ipr->RxFreeDesc--;
      mac_ipr->RxSuccCounter++;
      rxd_ptr = rxd_ptr->vndesc_ptr;
   }
   mac_ipr->rx_remove_ptr = rxd_ptr;
}

/* Allocate RX buffer */
void alloc_rx_buf(MAC_STRU *mac_ipr)
{
	int	io_base = mac_ipr->io_base;
   RDC_DESCRIPTOR *rxd_ptr = mac_ipr->rx_insert_ptr;

	while(mac_ipr->RxFreeDesc < DESC_COUNT) {
      outport(io_base + IO_MRDC, 0);
		rxd_ptr->status = 0x8000;
      mac_ipr->RxFreeDesc++;
      rxd_ptr = rxd_ptr->vndesc_ptr;
   }
   mac_ipr->rx_insert_ptr = rxd_ptr;
}

/* MAC1/2 interrupt 4 handler */
void _interrupt int4_handler(__CPPARGS)
{
	int	tmp_int;

   /* Got Host interrupt status */
   tmp_int = inport(INT_STATUS);

   if (tmp_int & MAC1_INT_REQ) mac_handler(&mac1_info);
   if (tmp_int & MAC2_INT_REQ) mac_handler(&mac2_info);

   /* EOI */
   outport(INTC_EOI, INT4_TYPE);
}

/* MAC interrupt handler for TX/RX */
void mac_handler(MAC_STRU *mac_ipr)
{
	int io_base = mac_ipr->io_base;
   unsigned int mac_int_status;

   /* Disable MAC interrupt */
   outport(io_base + IO_MIMR, 0);

   /* Get MAC interrupt status */
   mac_int_status = inport(io_base + IO_MISR);

   /* Handle MAC TX/RX interrupt request */
   if (mac_int_status & INT_TXEE) mac_tx_handler(mac_ipr);
   if (mac_int_status & INT_RXEE) mac_rx_handler(mac_ipr);

  /* Re-enable MAC nterrupt */
  outport(io_base + IO_MIMR, INT_TXEE + INT_RXEE);
}

/* MAC TX interrupt handler */
void mac_tx_handler(MAC_STRU *mac_ipr)
{
	MAC_STRU *next_mac = mac_ipr->next_mac;
   int io_base = next_mac->io_base;
   RDC_DESCRIPTOR *txd_ptr = mac_ipr->tx_remove_ptr;
   RDC_DESCRIPTOR *rxd_ptr = next_mac->rx_insert_ptr;

   while(mac_ipr->TxFreeDesc < DESC_COUNT) {
   	if (txd_ptr->status & 0x8000) break;
      txd_ptr = txd_ptr->vndesc_ptr;
      mac_ipr->TxFreeDesc++;
      mac_ipr->TxSuccCounter++;

      /* Re-use RX desciptor */
		rxd_ptr->status = 0x8000;
      outport(io_base + IO_MRDC, 0);	/* Trigger MAC increase RX descriptor count */
      next_mac->RxFreeDesc++;
      rxd_ptr = rxd_ptr->vndesc_ptr;
	}
   mac_ipr->tx_remove_ptr = txd_ptr;
   next_mac->rx_insert_ptr = rxd_ptr;
}

/* MAC RX interrupt handler */
void mac_rx_handler(MAC_STRU *mac_ipr)
{
	MAC_STRU *next_mac = mac_ipr->next_mac;
	int io_base = next_mac->io_base;
   RDC_DESCRIPTOR *rxd_ptr = mac_ipr->rx_remove_ptr;
   RDC_DESCRIPTOR *txd_ptr = next_mac->tx_insert_ptr;

   while(mac_ipr->RxFreeDesc) {
   	if (rxd_ptr->status & 0x8000) break;
		mac_ipr->RxFreeDesc--;
      mac_ipr->RxSuccCounter++;

      /* Another MAC send */
      txd_ptr->len = rxd_ptr->len - 4;		/* Skip 4 byte CRC */
      txd_ptr->status = 0x8000;
      outport(io_base + IO_MTPR, 1);
      next_mac->TxFreeDesc--;

      /* Next descriptor */
      rxd_ptr = rxd_ptr->vndesc_ptr;
      txd_ptr = txd_ptr->vndesc_ptr;
   }
   mac_ipr->rx_remove_ptr = rxd_ptr;
   next_mac->tx_insert_ptr = txd_ptr;
}



void delaye(void)
{
     int i;
     for (i=0;i<8000;i++)
     {
       Loops();
     }
}

void Loops(void)
{
     int i;
     for (i=0;i<80;i++)
     {
       asm nop;
       asm nop;
       asm nop;
       asm nop;
     }
}
void FlashLed(void)
{
    int StartLed=1;
    	
    int i;

    for (i=0; i<8; i++)
    {
        outport(0x80, StartLed);
        StartLed <<=1;
        delaye();
    }

}
/* UART0 interrupt handler */
void _interrupt uart0_handler(__CPPARGS)
{
	unsigned char tmpv;

   /* Clear UART0 interrupt status */
   tmpv = inport(0xff84);	/* IIR to prevent TX Empty interrupt */

   /* Check UART0 status*/
  	tmpv = inport(0xff8a);	/* UART0 status */
   if (tmpv & 0x01) {
     	tmpv = inport(0xff80);	/* Received data */
      switch (tmpv)
      {
       case 0x55:
       outport(0xff7a, 0x0800);
		 delaye();
       outport(0xff7a, 0x1800);
		 delaye();
       outport(0xff7a, 0x3800);
		 delaye();
       outport(0xff7a, 0x7800);
       break;
       case 0xaa:
       outport(0xff7a, 0x7000);
		 delaye();
       outport(0xff7a, 0x3000);
		 delaye();
       outport(0xff7a, 0x1000);
		 delaye();
       outport(0xff7a, 0x0000);
       break;
       case 0x80:
       outport(0xffe6, 0x3333);		/* Watch-dog Timer write sequence */
 	    outport(0xffe6, 0xcccc);		/* Watch-dog Timer write sequence */
 	    outport(0xffe6, 0x9080);		/* Enable Watch-dog timer for 1.342s*/
       break;
       default:
       break;
      }

      outport(0xff80, tmpv);	/* Send Data */
      PutStr(0,"<<==Response Code\r\n");
	}

   /* EOI */
   outport(INTC_EOI, 0x8000);
}

void _interrupt uart1_handler(__CPPARGS)
{
	unsigned char tmpv1;
	
	 /* Clear UART1 interrupt status */
   tmpv1 = inport(0xff14);	/* IIR to prevent TX Empty interrupt */

   /* Check UART1 status*/
  	tmpv1 = inport(0xff1a);	/* UART0 status */
   if (tmpv1 & 0x01) {
   	
     	tmpv1 = inport(0xff10);	/* Received data */
      outport(0xff10, tmpv1);	/* Send Data */
      PutStr(1,"<<==Response Code\r\n");
	}

   /* EOI */
   outport(INTC_EOI, 0x8000);
}

void PutStr(int p,char *pstr)
{
	while(*pstr!='\0')
    {
    	PutCh(p,*pstr++);
    }
}

void PutCh(int p,char ch)
{
	unsigned char	tmp;
    unsigned int	base;

    base=(p==0)?UARTBASE0:UARTBASE1;

    while(1)
    {
    	tmp=inportb(base+10);
        if(tmp&0x20)
        {
        	outportb(base,ch);
        	return;
        }
    }
}