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/* R1620 MAC Driver include file for Paradigm C */
/* PHY N-WAY capability */
#define NWAY_10H 0x0020
#define NWAY_10F 0x0040
#define NWAY_100H 0x0080
#define NWAY_100F 0x0100
/* R1620 I/O map define */
/* BUS Control Register */
#define CPU_BUS_CTRL 0xFFEA
/* 8259 Interrupt Controller */
#define INTC_EOI 0xFF22
#define INT_STATUS 0xFF30
#define INTC_INT0 0xFF38
#define INTC_INT1 0xFF3A
#define INTC_INT4 0xFF40
#define INT0_TYPE 0x0C
#define INT1_TYPE 0x0D
#define INT4_TYPE 0x10
#define MAC1_INT_REQ 0x0110
#define MAC2_INT_REQ 0x0220
/* SDRAM Controller I/O address */
#define SDRAM_ARBITER 0xFEF0
#define SDRAM_MODE 0xFEF2
#define SDRAM_CONTROL 0xFEF4
#define SDRAM_TIMEING 0xFEF6
/* TIMER I/O address */
#define TIMER2_CR 0xFF60
#define TIMER2_MCAR 0xFF62
#define TIMER2_MCR 0xFF66
/* DMA I/O address */
#define DMA0_SAL 0xFFC0
#define DMA0_SAH 0xFFC2
#define DMA0_DAL 0xFFC4
#define DMA0_DAH 0xFFC6
#define DMA0_TCR 0xFFC8
#define DMA0_CR 0xFFCA
#define DMA1_SAL 0xFFD0
#define DMA1_SAH 0xFFD2
#define DMA1_DAL 0xFFD4
#define DMA1_DAH 0xFFD6
#define DMA1_TCR 0xFFD8
#define DMA1_CR 0xFFDA
/* PIO */
#define PIO_DATA1_REG 0x0FF7A /* PIO data 1 register */
/* MAC I/O Base Address define */
#define MAC0_IO_BASE 0xFD00
#define MAC1_IO_BASE 0xFE00
#define MAC_IO MAC0_IO_BASE + 0x100 * MAC_SEL
/* MAC register I/O define */
enum R1620_MAC_REG {
IO_MCR0=0x00, IO_MCR1=0x04, IO_MBCR=0x08, IO_MTICR=0x0C,
IO_MRICR=0x10, IO_MTPR=0x14, IO_MRBS=0x18, IO_MRDC=0x1A, IO_MSR=0x1C,
IO_MMDIO=0x20, IO_MMRD=0x24, IO_MMWD=0x28,
IO_MTDSR0=0x2C, IO_MTDSR1=0x30, IO_MRDSR0=0x34, IO_MRDSR1=0x38,
IO_MISR=0x3C, IO_MIMR=0x40, IO_MIESR=0x44, IO_MIEMR=0x48,
IO_MRCNT=0x50, IO_MECNT0=0x52, IO_MECNT1=0x54, IO_MECNT2=0x56,
IO_MECNT3=0x58, IO_MTCNT=0x5A, IO_MECNT4=0x5C, IO_MPCNT=0x5E,
IO_MAR0=0x60, IO_MAR1=0x62, IO_MAR2=0x64, IO_MAR3=0x66,
IO_MID0L=0x68, IO_MID0M=0x6A, IO_MID0H=0x6C, IO_MID1L=0x70, IO_MID1M=0x72, IO_MID1H=0x74,
IO_MID2L=0x78, IO_MID2M=0x7A, IO_MID2H=0x7C, IO_MID3L=0x80, IO_MID3M=0x82, IO_MID3H=0x84,
IO_MTSCF=0xAC, IO_MTSCR=0xAE, IO_MTSTF=0xB0, IO_MTSRF=0xB2, IO_MTSRS=0xB4
};
/* PHY COMMAND */
#define MIIWR 0x4000
#define MIIRD 0x2000
#define PHY1_ADDR 0x0100
#define PHY2_ADDR 0x0200
/* MAC Control Register 0 */
#define MC_FULLD 0x8000 /* Full Duplex */
#define MC_ETX 0x4000 /* TX early function */
#define MC_XMTEN 0x1000 /* TX enable */
#define MC_FCEN 0x0200 /* Flow Control */
#define MC_AM 0x0100 /* Hash Function */
#define MC_ERX 0x0080 /* RX early function */
#define MC_FBCP 0x0040 /* Skip broadcast packet*/
#define MC_PRO 0x0020 /* RX all Frame */
#define MC_ADRB 0x0010 /* RX Dribble Frame */
#define MC_ALONG 0x0008 /* RX Long Frame */
#define MC_ARUNT 0x0004 /* RX Runt Frame */
#define MC_ACRCER 0x0001 /* RX CRC Frame */
#define MC_RCVEN 0x0002 /* RX enable */
/* MAC Control Register 1 */
#define MC_TPF 0x0200 /* Pause Frame send */
#define MC_ECR 0x0100 /* Excessive Collision Retry-32 */
#define MC_EITH0 0x0000 /* Early interrupt Threshols 1129 */
#define MC_EITH1 0x0040 /* Early interrupt Threshols 1257 */
#define MC_EITH2 0x0080 /* Early interrupt Threshols 1385 */
#define MC_EITH3 0x00C0 /* Early interrupt Threshols 1513 */
#define MC_MXLEN0 0x0000 /* Long Frame selector 1537 */
#define MC_MXLEN1 0x0010 /* Long Frame selector 1518 */
#define MC_MXLEN2 0x0020 /* Long Frame selector 1522 */
#define MC_MXLEN3 0x0030 /* Long Frame selector 1534 */
#define MC_SUMEN 0x0008 /* Hardware check sum for IP/UDP/TCP */
#define MC_LBM 0x0002 /* Loopback mode */
#define MC_MRST 0x0001 /* Software Reset */
#define MC_NM 0x0000 /* Normal mode */
/* Bus Control Register */
#define BC_RHPT16 0x0000 /* Receive High Priority Threshold 16 */
#define BC_RHPT32 0x0040 /* Receive High Priority Threshold 32 */
#define BC_RHPT64 0x0080 /* Receive High Priority Threshold 64 */
#define BC_RHPT96 0x00C0 /* Receive High Priority Threshold 96 */
#define BC_RXMDTH8 0x0000 /* RX moving data threshold 8 */
#define BC_RXMDTH16 0x0010 /* RX moving data threshold 16 */
#define BC_RXMDTH32 0x0020 /* RX moving data threshold 32 */
#define BC_RXMDTH64 0x0030 /* RX moving data threshold 64 */
#define BC_XMTTH16 0x0000 /* TX Threshold 16 */
#define BC_XMTTH32 0x0004 /* TX Threshold 32 */
#define BC_XMTTH64 0x0008 /* TX Threshold 64 */
#define BC_XMTTH96 0x000C /* TX Threshold 96 */
#define BC_BLW4 0x0000 /* Burst Length Width 4 */
#define BC_BLW8 0x0001 /* Burst Length Width 8 */
#define BC_BLW16 0x0002 /* Burst Length Width 16 */
#define BC_BLW32 0x0003 /* Burst Length Width 32 */
/* MAC Last Status */
#define MS_UDRN 0x8000 /* TX FIFO under-run /*
#define MS_LATCOL 0x4000 /* TX late collision /*
#define MS_EXCOL 0x2000 /* TX excessived collision 32 times /*
#define MS_DESCUV 0x0400 /* RX descriptor unavailable /*
#define MS_FIFOOR 0x0200 /* RX FIFO over run /*
#define MS_RXERR 0x0080 /* RX PHY error /*
#define MS_DRIBBLE 0x0040 /* RX Dribble packet /*
#define MS_OBL 0x0020 /* RX received length over buffer size /*
#define MS_LONG 0x0010 /* RX Long frame /*
#define MS_RUNT 0x0008 /* RX Runt frame /*
#define MS_CRCERR 0x0004 /* RX CRC packet /*
#define MS_BC 0x0002 /* RX Broad-cast Frame /*
#define MS_MC 0x0001 /* RX Multi-cast Frame /*
/* RX descriptor status */
#define RXD_OK 0x4000
#define RXD_RXERR 0x0800
#define RXD_DRIBBLE 0x0400
#define RXD_OBL 0x0200
#define RXD_LONG 0x0100
#define RXD_RUNT 0x0080
#define RXD_CRCERR 0x0040
#define RXD_BC 0x0020
#define RXD_MC 0x0010
#define RXD_MCH 0x0008
#define RXD_IPSUM 0x0004
#define RXD_MID3 0x0003
#define RXD_MID2 0x0002
#define RXD_MID1 0x0001
#define RXD_MID0 0x0000
/* TX descriptor status */
#define TXD_COLCNT 0x000F
#define TXD_EXCOL 0x0010
#define TXD_LATCOL 0x0020
#define TXD_UDRN 0x0040
#define TXD_OK 0x4000
/* Interrupt mask */
#define INT_MCHGE 0x0200
#define INT_ECNTOE 0x0100
#define INT_ETXIE 0x0080
#define INT_TXEE 0x0010
#define INT_ERXIE 0x0008
#define INT_FOE 0x0004
#define INT_DUNAVE 0x0002
#define INT_RXEE 0x0001
/* Event interrupt Mask */
#define EINT_UR 0x0800
#define EINT_LC 0x0400
#define EINT_TXS 0x0200
#define EINT_FF 0x0100
#define EINT_DU 0x0080
#define EINT_LONG 0x0020
#define EINT_RUNT 0x0010
#define EINT_CRC 0x0008
#define EINT_BF 0x0004
#define EINT_MF 0x0002
#define EINT_RXS 0x0001
/* Test Mode control register */
#define TT_TXTH 0x0004
#define TT_FIFOT 0x0002
#define TT_CNTW 0x0001
#define TT_TXIMM 0x0000
/* Structure Define */
/* Descriptor Structure Define */
#define RDC_DESC_SIZE 0x20
typedef struct RDC_DESCRIPTOR {
uint16 status; /* 00h */
uint16 len; /* 02h */
uint32 buf_ptr; /* 04h */
uint32 ndesc_ptr; /* 08h */
uint16 reserved1; /* 0Ch */
uint16 reserved2; /* 0Eh */
uint16 reserved3; /* 10h */
char *vbuf_ptr; /* 12h */
struct RDC_DESCRIPTOR *vndesc_ptr;/* 16h */
uint16 rev0, rev1, rev2; /* 1Ah, 1Ch, 1Eh */
} RDC_DESCRIPTOR;
/* R1620 MAC information strcture */
typedef struct MAC_STRU {
RDC_DESCRIPTOR *tx_insert_ptr;
RDC_DESCRIPTOR *tx_remove_ptr;
RDC_DESCRIPTOR *rx_insert_ptr;
RDC_DESCRIPTOR *rx_remove_ptr;
struct MAC_STRU * next_mac;
char *tx_desc_ptr;
char *rx_desc_ptr;
uint32 txd_raddr;
uint32 rxd_raddr;
uint16 sn;
uint16 io_base;
uint16 int_status;
uint16 phy_addr;
uint16 StartBufPtr;
uint16 EndBufPtr;
uint16 SendBufferPtr;
uint16 TxStartLen;
uint16 TxEndLen;
uint16 TxRepCnt;
uint16 TxGap;
uint16 TxTmpLen;
uint16 TxTmpRep;
uint16 TxFreeDesc;
uint16 RxFreeDesc;
uint16 TmpRxSeq;
uint16 CtrlPktIn;
/* Hardware Statistic Counter for MAC */
uint32 HWTxSuccCnt;
uint32 HWTxPktLost;
uint32 HWTxLateCol;
uint32 HWRxSuccCnt;
uint32 HWRxBroadcast;
uint32 HWRxMulticast;
uint32 HWRxRuntFrame;
uint32 HWRxLongFrame;
uint32 HWRxCRCFrame;
uint32 HWRxCollision;
uint32 HWRxFifoFull;
uint32 HWRxDescUnv;
/* Software Statistic Counter for RX/TX descriptor status */
uint32 TxCount;
uint32 TxSuccCounter;
uint32 TxColliCounter;
uint32 TxExcesCounter;
uint32 TxLatecCounter;
uint32 TxUnderCounter;
uint32 TxJabberCounter;
uint32 RxByteCounter;
uint32 RxSuccCounter;
uint32 RxMultiFrameCounter;
uint32 RxBroadFrameCounter;
uint32 RxCRCCounter;
uint32 RxRuntCounter;
uint32 RxLongCounter;
uint32 RxOBLCounter;
uint32 RxDRICounter;
uint32 RxPHYCounter;
uint32 RxFullCounter;
uint32 RxLenCounter;
uint32 RxDataECounter;
uint32 RxPktSeqCounter;
} MAC_STRU;
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