usbhost.bak

来自「RDC R2886 USB Ehci ohc测试源码,paradigm c++上」· BAK 代码 · 共 483 行 · 第 1/2 页

// USB Host Controller test pattern include file
// Modification List:
// 05/19/2003    Jeff

#define USB_Port	0	//0 or 1

#define u8	unsigned char
#define u16 	unsigned short
#define u32 	unsigned long

#define PCBBase 		0xff00
//#define PCIBase			0x5000
#define USBBase   		0x6000

// ================ Peripheral Control Register Address =======================
#define INTACON_OFF		PCBBase+0x0048
#define INT_EOI			PCBBase+0x0022
#define INT_INSERV		PCBBase+0x002C

#define PIO_DATA1_REG		PCBBase+0x007A		// PIO data 1 register
// ============================================================================

// ================ 8259 Interrupt Controller =================================
#define INTA_TYPE       	0x0015
#define INTB_TYPE       	0x0016
#define INTC_TYPE       	0x0017
#define INTD_TYPE       	0x0018
#define UART1_TYPE		0x0011
#define UART0_TYPE		0x0014
// ============================================================================

// ================ UART1 Related Register =======================
#define RBR     	0x10    //Receiver Buffer Register as DLAB = 0 (Read Only)
#define THR     	0x10    //Transmitter Holding Register as DLAB = 0 (Write Only)
#define IER     	0x12    //Interrupt Enable Register as DLAB = 0
#define IIR     	0x14    //Interrupt Identification Register (Read Only)
#define FCR     	0x14    //FIFO Control Register (Write Only)
#define LCR     	0x16    //Line Control Register
#define MCR     	0x18    //MODEM Control Register
#define LSR     	0x1A    //Line Status Register
#define MSR     	0x1C    //MODEM Status Register
#define SCR     	0x1E    //Scratch Register
#define DLL     	0x10    //Divisor Latch Low Byte as DLAB = 1
#define DLM     	0x12    //Divisor Latch High Byte as DLAB = 1
//UART 0
/*#define RBR     	0x80    //Receiver Buffer Register as DLAB = 0 (Read Only)
#define THR     	0x80    //Transmitter Holding Register as DLAB = 0 (Write Only)
#define IER     	0x82    //Interrupt Enable Register as DLAB = 0
#define IIR     	0x84    //Interrupt Identification Register (Read Only)
#define FCR     	0x84    //FIFO Control Register (Write Only)
#define LCR     	0x86    //Line Control Register
#define MCR     	0x88    //MODEM Control Register
#define LSR     	0x8A    //Line Status Register
#define MSR     	0x8C    //MODEM Status Register
#define SCR     	0x8E    //Scratch Register
#define DLL     	0x80    //Divisor Latch Low Byte as DLAB = 1
#define DLM     	0x82    //Divisor Latch High Byte as DLAB = 1 */
//////////////////////////////////
#define DLABH   	0x80	//DLAB = 1
//#define BAUDDIVL 	0x36	//115200, 100MHz/16/115200=54=0x36
//#define BAUDDIVH 	0x00
//
//#define BAUDDIVL 	0x8b	//9600, 100MHz/16/9600=0x28b
//#define BAUDDIVH 	0x02
#define BAUDDIVL 	0x51	//9600, 133MHz/16/9600=0x28b
#define BAUDDIVH 	0x00
//#define BAUDDIVL 	0xd0	//9600, 150MHz/16/9600=0x3d0
//#define BAUDDIVH 	0x03
#define bitlen		0x03	//Character Length = 8 bits

//Line Status Register
#define DRI     	0x01     //Data Ready indicator
#define OEI     	0x02     //Overrun Error indicator
#define PEI     	0x04     //Parity Error indicator
#define FEI     	0x08     //Frame Error indicator
#define BII     	0x10     //Break Interrupt indicator
#define nTHRE   	0x20     //THR empty for the sake of checking empty of THR
#define nTEMT   	0x40     //To test if Transmitter Shift-Register is empty
#define LSR7    	0x80     //error in RCVR FIFO

//DMA ,for DnCON
#define DIO             0x0
#define DM              0x08000
#define DDEC            0x04000
#define DINC            0x02000
#define SM              0x01000
#define SIO             0x0
#define SDEC            0x00800
#define SINC            0x00400
#define TC              0x00200
#define DMAINT          0x00100
#define DMAP            0x00020
#define TDRQ            0x00010
#define DMAEXT          0x00008
#define DMAP0		0x00008
#define CHG             0x00004
#define DMAST           0x00002
#define DMAB            0x0
#define DMAW            0x00001

#define UnSYN           0x0
#define SrcSYN          0x040
#define DesSYN          0x080

/* DMA I/O address */
#define         DMA0_SAL        0xFFC0
#define         DMA0_SAH        0xFFC2
#define         DMA0_DAL        0xFFC4
#define         DMA0_DAH        0xFFC6
#define         DMA0_TCR        0xFFC8
#define         DMA0_CR         0xFFCA
#define         DMA1_SAL        0xFFD0
#define         DMA1_SAH        0xFFD2
#define         DMA1_DAL        0xFFD4
#define         DMA1_DAH        0xFFD6
#define         DMA1_TCR        0xFFD8
#define         DMA1_CR         0xFFDA
// ============================================================================

// ================ PCI Related Register =======================
#define PCI_DWAAL_REG   0xFF00
#define PCI_DWAAH_REG   0xFF02
#define PCI_DWADL_RQG   0xFF04
#define PCI_DWADH_RQG   0xFF06
#define PCI_CFGAL_REG   0xFF08
#define PCI_CFGAH_REG   0xFF0A
#define PCI_CFGDL_RQG   0xFF0C
#define PCI_CFGDH_RQG   0xFF0E
// ============================================================================

// ================ PCI Bridge Control Register Address =======================
#define B_MemBasAddr		0x0040
#define B_MemBasAddrMask	0x0044
#define B_IOBasAddr		0x0048
#define B_IOBasAddrMask		0x004C
// ============================================================================

// ================ Device Configulation Register Address =====================
//Set to Device 1
#define DCR_VID			0x0000
#define DCR_DID			0x0002
#define DCR_Command		0x0004
#define DCR_Status		0x0006
#define DCR_Revision		0x0008
#define DCR_ClassCodeL		0x0009
#define DCR_ClassCodeH		0x000A
#define DCR_CLS			0x000C
#define DCR_LT			0x000D
#define DCR_Header		0x000E
#define DCR_Bist		0x000F
#define DCR_BAL			0x0010
#define DCR_BAH			0x0012
#define DCR_SubsysVID		0x002C
#define DCR_SubsysDID		0x002E
#define DCR_CAPPTR		0x0034
#define DCR_IL			0x003C
#define DCR_IP			0x003D
#define DCR_MG			0x003E
#define DCR_ML			0x003F
#define DCR_TM1L		0x0040
#define DCR_TM1H		0x0042
#define DCR_TM2L		0x0044
#define DCR_TM2H		0x0046
#define DCR_TM3L		0x0048
#define DCR_TM3H		0x004A
#define DCR_CAPID		0x0050
#define DCR_NIP			0x0051
#define DCR_PMC			0x0052
#define DCR_PMCSR		0x0054
#define DCR_PMCSR_BSE		0x0056
#define DCR_DATAR		0x0057
#define DCR_CAPID_1		0x0058
#define DCR_NIP_1		0x0059
#define DCR_DPCR		0x005A
#define DCR_SBRN		0x0060
#define DCR_FLA			0x0061
#define DCR_PWCR		0x0062
#define DCR_USB_LSECL		0x0070
#define DCR_USB_LSECH		0x0072
#define DCR_USB_LSCSRL		0x0074
#define DCR_USB_LSCSRH		0x0076

// ============================================================================

// ================ System Init Parameter =====================================
#define SHADOW_FLAG     0x0000	// 0:Disable shadow, 1:enable shadow
#define CACHE_CTRL      0xC780  // 0:Disable Cache, B15:I-C En, B14:D-C En, B13:WB, B12:NCFE, B11:NCR3E, B10:NCR2E, B9:NCR1E, B8:NCR0E, B7:WIRE
#define REFRESH_COUNT     1000  // FFE2h: 100 host clock, 13.3us at 7.5Mhz
                                // 1000 host clock, 13.3us at 75Mhz
#define ARBITER_CONTROL 0x0001  // FEF0h: SDRAM Arbiter control B4:0 re-fresh priority
#define SDRAM_MODE_SET  0x0030  // FEF2h, CAS latency 3
#define SDRAM_CTRL      0x0009  // FEF4h, 4M*16, SDRAM enable, Bit5 APC, Bit4-3 SDRAM Type, Bit0 SDRAM enable
#define SDRAM_TIMING    0xFB35  // FEF6h, Tsrx 15clk, Mrc 9clk, Mpc 3clk, RCD 3clk

#define UCS_CONTROL     0xC03A  // UCS Control Register 0FFA0h
                                // 256Kbyte, 3 wait-state. Others 0~768K LCS
#define LCS_CONTROL     0x7000  // PCS 512K SDRAM
#define MUL_CONTROL     0x0004  // LCS size * 16, UCS size * 1, PCS size * 1
#define GLOBAL_SETTING  0x0001  // 0:Local setting, 1:Global setting
#define SHADOW_SIZE     0xF000  // Shadow Code size 10K byte
#define CRC_PASS        0x0001  // 0: MAC re-calculate CRC, 1: Directly pass CRC
#define LOOPTEST        0x0000  // 1:Loop test until pattern fail, 0:Test one time
#define WORDBOUNDARY    0x0000  // 0: Set desc/buf in DWORD boundary, 1: Set it in WORD boundary
#define DWORDOUTPORT	0x0001	// 0: Set for WORD outport mode, 1: Set for DWORD outport mode

#define PIO_MODE1_SET   0x0  // PIO mode config: PIO 22,23,24, other normal
// ============================================================================

/*-------------------------------------------------------------------------*/

/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */

/* Section 2.2 Host Controller Capability Registers */
typedef __far struct ehci_capability {
	u8		length;		/* CAPLENGTH - size of this struct */
	u8		reserved;       /* offset 0x1 */
	u16		hci_version;    /* HCIVERSION - offset 0x2 */
	u32		hcs_params;     /* HCSPARAMS - offset 0x4 */
#define HCS_DEBUG_PORT(p)	(((p)>>20)&0xf)	/* bits 23:20, debug port? */
#define HCS_INDICATOR(p)	((p)&(1 << 16))	/* true: has port indicators */
#define HCS_N_CC(p)		(((p)>>12)&0xf)	/* bits 15:12, #companion HCs */
#define HCS_N_PCC(p)		(((p)>>8)&0xf)	/* bits 11:8, ports per CC */
#define HCS_PORTROUTED(p)	((p)&(1 << 7))	/* true: port routing */ 
#define HCS_PPC(p)		((p)&(1 << 4))	/* true: port power control */ 
#define HCS_N_PORTS(p)		(((p)>>0)&0xf)	/* bits 3:0, ports on HC */

	u32		hcc_params;      /* HCCPARAMS - offset 0x8 */
#define HCC_EXT_CAPS(p)		(((p)>>8)&0xff)	/* for pci extended caps */
#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
#define HCC_CANPARK(p)		((p)&(1 << 2))  /* true: can park on async qh */
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
	u8		portroute [8];	 /* nibbles for routing - offset 0xC */
}ehci_capability;


/* Section 2.3 Host Controller Operational Registers */
typedef __far struct ehci_registers {

	/* USBCMD: offset 0x00 */
	u32		command;