usbhost.bak

来自「RDC R2886 USB Ehci ohc测试源码,paradigm c++上」· BAK 代码 · 共 483 行 · 第 1/2 页

/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
#define CMD_PARK	(1<<11)		/* enable "park" on async qh */
#define CMD_PARK_CNT(c)	(((c)>>8)&3)	/* how many transfers to park for */
#define CMD_LRESET	(1<<7)		/* partial reset (no ports, etc) */
#define CMD_IAAD	(1<<6)		/* "doorbell" interrupt async advance */
#define CMD_ASE		(1<<5)		/* async schedule enable */
#define CMD_PSE  	(1<<4)		/* periodic schedule enable */
/* 3:2 is periodic frame list size */
#define CMD_RESET	(1<<1)		/* reset HC not bus */
#define CMD_RUN		(1<<0)		/* start/stop HC */

	/* USBSTS: offset 0x04 */
	u32		status;
#define STS_ASS		(1<<15)		/* Async Schedule Status */
#define STS_PSS		(1<<14)		/* Periodic Schedule Status */
#define STS_RECL	(1<<13)		/* Reclamation */
#define STS_HALT	(1<<12)		/* Not running (any reason) */
/* some bits reserved */
	/* these STS_* flags are also intr_enable bits (USBINTR) */
#define STS_IAA		(1<<5)		/* Interrupted on async advance */
#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
#define STS_FLR		(1<<3)		/* frame list rolled over */
#define STS_PCD		(1<<2)		/* port change detect */
#define STS_ERR		(1<<1)		/* "error" completion (overflow, ...) */
#define STS_INT		(1<<0)		/* "normal" completion (short, ...) */

	/* USBINTR: offset 0x08 */
	u32		intr_enable;

	/* FRINDEX: offset 0x0C */
	u32		frame_index;	/* current microframe number */
	/* CTRLDSSEGMENT: offset 0x10 */
	u32		segment; 	/* address bits 63:32 if needed */
	/* PERIODICLISTBASE: offset 0x14 */
	u32		frame_list; 	/* points to periodic list */
	/* ASYNCICLISTADDR: offset 0x18 */
	u32		async_next;	/* address of next async queue head */

	u32		reserved [9];

	/* CONFIGFLAG: offset 0x40 */
	u32		configured_flag;
#define FLAG_CF		(1<<0)		/* true: we'll support "high speed" */

	/* PORTSC: offset 0x44 */
	u32		port_status[6];	/* up to N_PORTS */
/* 31:23 reserved */
#define PORT_WKOC_E	0x00400000L		/* wake on overcurrent (enable) */
#define PORT_WKDISC_E	0x00200000L		/* wake on disconnect (enable) */
#define PORT_WKCONN_E	0x00100000L		/* wake on connect (enable) */
/* 19:16 for port testing */
#define PORT_Test_J		0x00010000L
#define PORT_Test_K		0x00020000L
#define PORT_Test_SE0_NAK	0x00030000L
#define PORT_Test_Packet	0x00040000L
#define PORT_Test_FORCE_ENABLE	0x00050000L
/* 15:14 for using port indicator leds (if HCS_INDICATOR allows) */
#define PORT_OWNER	(1<<13)		/* true: companion hc owns this port */
#define PORT_POWER	(1<<12)		/* true: has power (see PPC) */
#define PORT_USB11(x) (((x)&(3<<10))==(1<<10))	/* USB 1.1 device */
/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
#define PORT_LineStatus	0x0C00
#define PORT_J_State	0x0800
#define PORT_K_State	0x0400
/* 9 reserved */
#define PORT_RESET	(1<<8)		/* reset port */
#define PORT_SUSPEND	(1<<7)		/* suspend port */
#define PORT_RESUME	(1<<6)		/* resume it */
#define PORT_OCC	(1<<5)		/* over current change */
#define PORT_OC		(1<<4)		/* over current active */
#define PORT_PEC	(1<<3)		/* port enable change */
#define PORT_PE		(1<<2)		/* port enable */
#define PORT_CSC	(1<<1)		/* connect status change */
#define PORT_CONNECT	(1<<0)		/* device connected */
/*
	u32		reserve [5];
	// DebugCtlSts: offset 0x90
	u32		DebugCtlSts;
	u32		DebugUSBPID;
	u32		DebugDatBuf0;
	u32		DebugDatBuf1;
	u32		DebugDevAdr;
*/
}ehci_registers;


/*-------------------------------------------------------------------------*/

/*
 * EHCI Specification 0.95 Section 3.6
 * QH: describes control/bulk/interrupt endpoints
 * See Fig 3-7 "Queue Head Structure Layout".
 *
 * These appear in both the async and (for interrupt) periodic schedules.
 */

typedef __far struct ehci_qh {
	/* first part defined by EHCI spec */
	u32			hw_next;	 /* see EHCI 3.6.1 */
#define QH_Typ_QH	0x02

	u32			hw_info1;        /* see EHCI 3.6.2 */
#define QH_RL		0xF0000000L
#define	QH_HEAD		0x00008000
#define QH_DTC_QH	0x00000000
#define QH_DTC_TD	0x00004000
#define QH_EPS		0x00002000
#define QH_EndPt_0	0x00000000
#define QH_EndPt_1	0x00000100
#define QH_EndPt_2	0x00000200
#define QH_DAddr	0x00000001

	u32			hw_info2;        /* see EHCI 3.6.2 */
#define QH_Mult		0x40000000L

	u32			hw_current;	 /* qtd list - see EHCI 3.6.4 */
	
	/* qtd overlay (hardware parts of a struct ehci_qtd) */
	u32			hw_qtd_next;
	u32			hw_alt_next;
	u32			hw_token;
#define	QH_IOC		0x00008000	/* interrupt on complete */	

	u32			hw_buf [5];

#define	QH_STATE_LINKED		1		/* HC sees this */
#define	QH_STATE_UNLINK		2		/* HC may still see this */
#define	QH_STATE_IDLE		3		/* HC doesn't see this */
#define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on reclaim q */
#define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
}ehci_qh;

/*-------------------------------------------------------------------------*/

/*
 * EHCI Specification 0.95 Section 3.5
 * QTD: describe data transfer components (buffer, direction, ...) 
 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 *
 * These are associated only with "QH" (Queue Head) structures,
 * used with control, bulk, and interrupt transfers.
 */
typedef __far struct ehci_qtd {
	/* first part defined by EHCI spec */
	u32			hw_next;	  /* see EHCI 3.5.1 */
	u32			hw_alt_next;      /* see EHCI 3.5.2 */
	u32			hw_token;         /* see EHCI 3.5.3 */       
#define	QTD_TOGGLE	(0x80000000L)	/* data toggle */
#define	QTD_LENGTH(tok)	(((tok)<<16) & 0x7fff)
#define	QTD_IOC		(0x00008000)	/* interrupt on complete */
#define QTD_CERR_3	(0x0C00)
#define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
#define	QTD_PID(tok)	(((tok)>>8) & 0x3)
#define QTD_PID_OUT	0x0000
#define QTD_PID_IN	0x0100
#define QTD_PID_SETUP	0x0200
#define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
#define	QTD_STS_HALT	(1 << 6)	/* halted on error */
#define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
#define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
#define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
#define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
#define	QTD_STS_STS	(1 << 1)	/* split transaction state */
#define	QTD_STS_PING	(1 << 0)	/* issue PING? */
	u32			hw_buf [5];        /* see EHCI 3.5.4 */
}ehci_qtd;


// ================ Device Descriptor Structure ==================
typedef __far struct setup_format
{
	u8 bmRequestType;
	u8 bRequest;
	u16 wValue;
	u16 wIndex;
	short wLength;
}setup_format;

typedef __far struct std_dev_des
{
	u8	bLength;
	u8	bDescriptorType;
	u16	bcdUSB;
	u8	bDeviceClass;
	u8	bDeviceSubClass;
	u8	bDeviceProtocal;
	u8	bMaxPacketSize;
	u16	idVendor;
	u16	idProduct;
	u16 bcdDevice;
	u8	iManufacturer;
	u8	iProduct;
	u8	iSerialNumber;
	u8	bNumConfigurations;
}std_dev_des;

typedef __far struct std_cfg_des
{
	u8	bLength;
	u8	bDescriptorType;
	u16	wTotalLength;
	u8	bNumInterfaces;
	u8	bConfigurationValue;
	u8	iConfiguration;
	u8	bmAttributes;
	u8	MaxPower;
}std_cfg_des;

typedef __far struct std_if_des
{
	u8	bLength;
	u8	bDescriptorType;
	u8	bInterfaceNumber;
	u8	bAlternateSetting;
	u8	bNumEndpoints;
	u8	bInterfaceClass;
	u8	bInterfaceSubClass;
	u8	bInterfaceProtocol;
	u8	iInterface;
}std_if_des;

typedef __far struct std_edp_des
{
	u8	bLength;
	u8	bDescriptorType;
	u8	bEndpointAddress;
	u8	bmAttributes;
	u16	wMaxPacketSize;
	u8	bInterval;
}std_edp_des;
// ============================================================================

// ================ TD Status ==================
//Set 1 -> enable TD, 0 -> TD in the donehead
#define St_CBW_TD	0x0001
#define St_CSW_TD	0x0002
#define St_DataIn_TD	0x0004
#define St_DataOut_TD	0x0008

// ================  ==================
// ============================================================================