fifo.v

一个同步FIFO

`timescale 1ns/1ps

module fifo(
	reset,
	clkw,
	clkr,
	din,
	web,
	dout,
	reb,
	full,
	empty);
	
parameter DATA_SIZE = 8;
parameter FIFO_DEPTH = 8;
	
input reset;
input clkw;
input clkr;
input [DATA_SIZE-1:0] din;
input web;
input reb;
output full;
output empty;
output [DATA_SIZE-1:0] dout;

reg full;
reg empty;
reg [DATA_SIZE-1:0] dout;

reg [DATA_SIZE-1:0] mem [0:FIFO_DEPTH-1];

integer write_addr,read_addr;
reg [DATA_SIZE-1:0] wr_data,rd_data;
integer data_count;
	
//write flip flop
always @(posedge clkw, reset)
	if (reset == 1'b1)
		wr_data <= 8'h00;
	else if (web == 1'b1)	
		wr_data <= din;

//write flip flop
always @(posedge clkr, reset)
	if (reset == 1'b1)
		rd_data <= 8'h00;
	else if (reb == 1'b1)	
		rd_data <= din;

always @(posedge clkw, web)
	if (web == 1'b1)
		mem[write_addr] <= din;
		
always @(posedge clkr, reb)
	if (reb == 1'b1)
		dout <= mem[read_addr];
	
//write address counter		
always @(posedge clkw, web, reset)
	if (reset == 1'b1)
		write_addr <= 0;
	else if (web == 1'b1)
	begin
		if (write_addr < (FIFO_DEPTH -1))
			write_addr <= write_addr + 1;
		else
			write_addr <= 0;
	end
	
//read address counter		
always @(posedge clkr, reb, reset)
	if (reset == 1'b1)
		read_addr <= 0;
	else if (reb == 1'b1)
	begin
		if (read_addr < (FIFO_DEPTH -1))
			read_addr <= read_addr + 1;
		else
			read_addr <= 0;
	end
	
//data counter	
always @(posedge clkr, reset)
	if (reset == 1'b1)
		data_count <= 0;
	else if (web == 1'b1 & reb == 1'b0)	
		data_count <= data_count + 1;
	else if (web == 1'b0 & reb == 1'b1)	
		data_count <= data_count - 1;

//full 
always @(posedge clkr, reset,data_count)
	if (reset == 1'b1)
		full <= 1'b0;
	else if (data_count == FIFO_DEPTH)
		full <= 1'b1;
	else
		full <= 1'b0;
	 		
//empty 
always @(posedge clkr, reset,data_count)
	if (reset == 1'b1)
		empty <= 1'b1;
	else if (data_count == 0)
		empty <= 1'b1;
	else
		empty <= 1'b0;
		
endmodule