tb.v

来自「一个同步FIFO」· Verilog 代码 · 共 49 行

`timescale 1ns/1ps
module testbench();
parameter DATA_SIZE = 8;
parameter FIFO_DEPTH = 16;

reg reset;
reg clk;
reg [DATA_SIZE-1:0] din;
reg web;
reg reb;
reg full;
reg empty;
reg [DATA_SIZE-1:0] dout;

	fifo #(
		DATA_SIZE,
		FIFO_DEPTH)
	fifo0 (
	reset,
	clk,
	clk,
	din,
	web,
	dout,
	reb,
	full,
	empty);

initial 
begin
	reset <= 1'b0;
	#5;
	reset <= 1'b1;
	#5;
	reset <= 1'b0;
end

initial 
begin
end 

initial 
forever
begin
	clk <= 1'b0; #5; clk <= 1'b1; #5; 
	
end
endmodule