edukit2.rpt

在三星ＡＲＭ２４１０嵌入式开发板上

edukit2

** EQUATIONS **

AB0      : INPUT;
AB1      : INPUT;
AB2      : INPUT;
AB3      : INPUT;
AB20     : INPUT;
AB21     : INPUT;
AB22     : INPUT;
AB23     : INPUT;
AB24     : INPUT;
BnOE     : INPUT;
BnWE     : INPUT;
CAN_INT  : INPUT;
CF_CD    : INPUT;
CF_INT   : INPUT;
CLKPUT0  : INPUT;
EX_IN0   : INPUT;
EX_IN1   : INPUT;
EX_IN2   : INPUT;
GPB9     : INPUT;
GPB10    : INPUT;
IDE_DMARQ : INPUT;
IDE_INT  : INPUT;
IDE_RDY  : INPUT;
NFCE     : INPUT;
nFRE     : INPUT;
nFWE     : INPUT;
nGCS1    : INPUT;
nGCS2    : INPUT;
nGCS3    : INPUT;
nGCS4    : INPUT;
nOE      : INPUT;
nRESET   : INPUT;
nWAIT    : INPUT;
PS2_INT1 : INPUT;
PS2_INT2 : INPUT;
PS2_IO2  : INPUT;
TSP_INT  : INPUT;

-- Node name is 'CAN_CS' 
-- Equation name is 'CAN_CS', location is LC033, type is output.
 CAN_CS  = LCELL( _EQ001 $  VCC);
  _EQ001 =  AB20 & !AB21 & !AB22 & !nGCS1;

-- Node name is 'CF_CSEL' = '|latch:281|OUT2' 
-- Equation name is 'CF_CSEL', type is output 
 CF_CSEL = DFFE( DB1 $  GND,  _EQ002,  VCC,  VCC,  VCC);
  _EQ002 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'CF_CS0' 
-- Equation name is 'CF_CS0', location is LC013, type is output.
 CF_CS0  = LCELL( _EQ003 $  VCC);
  _EQ003 = !AB20 &  AB21 & !AB22 & !nGCS1;

-- Node name is 'CF_CS1' 
-- Equation name is 'CF_CS1', location is LC009, type is output.
 CF_CS1  = LCELL( _EQ004 $  VCC);
  _EQ004 =  AB20 &  AB21 & !AB22 & !nGCS1;

-- Node name is 'CF_IORD' 
-- Equation name is 'CF_IORD', location is LC005, type is output.
 CF_IORD = LCELL( _EQ005 $  VCC);
  _EQ005 = !AB20 & !AB21 &  AB22 & !BnOE & !nGCS2;

-- Node name is 'CF_IOWR' 
-- Equation name is 'CF_IOWR', location is LC003, type is output.
 CF_IOWR = LCELL( _EQ006 $  VCC);
  _EQ006 = !AB20 & !AB21 &  AB22 & !BnWE & !nGCS2;

-- Node name is 'CF_MMRD' 
-- Equation name is 'CF_MMRD', location is LC008, type is output.
 CF_MMRD = LCELL( _EQ007 $  VCC);
  _EQ007 =  AB20 &  AB21 & !AB22 & !BnOE & !nGCS2;

-- Node name is 'CF_MMWR' 
-- Equation name is 'CF_MMWR', location is LC030, type is output.
 CF_MMWR = LCELL( _EQ008 $  VCC);
  _EQ008 =  AB20 &  AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'CF_WAIT' = '|latch:281|OUT1' 
-- Equation name is 'CF_WAIT', type is output 
 CF_WAIT = DFFE( DB0 $  GND,  _EQ009,  nUSB_EN,  VCC,  VCC);
  _EQ009 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'CPLD_INT1' 
-- Equation name is 'CPLD_INT1', location is LC128, type is output.
 CPLD_INT1 = LCELL( TSP_INT $  GND);

-- Node name is 'CPLD_INT2' 
-- Equation name is 'CPLD_INT2', location is LC126, type is output.
 CPLD_INT2 = LCELL( _EQ010 $  GND);
  _EQ010 =  CAN_INT &  CF_INT &  IDE_INT &  PS2_INT2;

-- Node name is 'CPLD_NFRE' 
-- Equation name is 'CPLD_NFRE', location is LC037, type is output.
 CPLD_NFRE = LCELL( _EQ011 $  VCC);
  _EQ011 =  AB20 & !AB21 &  AB22 & !BnOE & !nGCS2;

-- Node name is 'CPLD_NFWE' 
-- Equation name is 'CPLD_NFWE', location is LC040, type is output.
 CPLD_NFWE = LCELL( _EQ012 $  VCC);
  _EQ012 =  AB20 & !AB21 &  AB22 & !BnWE & !nGCS2;

-- Node name is 'DB0' 
-- Equation name is 'DB0', location is LC107, type is bidir.
DB0      = TRI(_LC107,  _LC043);
_LC107   = LCELL( _EQ013 $  VCC);
  _EQ013 = !AB20 &  AB21 & !AB22 & !BnOE & !CF_INT & !nGCS2
         #  AB20 & !AB21 & !AB22 & !BnOE & !nGCS2 & !PS2_IO2;

-- Node name is 'DB1' 
-- Equation name is 'DB1', location is LC105, type is bidir.
DB1      = TRI(_LC105,  _LC043);
_LC105   = LCELL( _EQ014 $  VCC);
  _EQ014 = !AB20 &  AB21 & !AB22 & !BnOE & !IDE_INT & !nGCS2
         #  AB20 & !AB21 & !AB22 & !BnOE & !CF_CD & !nGCS2;

-- Node name is 'DB2~1' 
-- Equation name is 'DB2~1', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( _EQ015 $  GND);
  _EQ015 = !AB22 & !BnOE & !nGCS2 &  _X001 &  _X002;
  _X001  = EXP(!AB20 & !AB21);
  _X002  = EXP( AB20 &  AB21);

-- Node name is 'DB2' 
-- Equation name is 'DB2', location is LC104, type is bidir.
DB2      = TRI(_LC104,  _LC043);
_LC104   = LCELL( _EQ016 $  VCC);
  _EQ016 =  AB20 & !AB21 & !AB22 & !BnOE & !IDE_RDY & !nGCS2
         # !AB20 &  AB21 & !AB22 & !BnOE & !nGCS2 & !PS2_INT2;

-- Node name is 'DB3' 
-- Equation name is 'DB3', location is LC102, type is bidir.
DB3      = TRI(_LC102,  _LC043);
_LC102   = LCELL( _EQ017 $  VCC);
  _EQ017 = !AB20 &  AB21 & !AB22 & !BnOE & !CAN_INT & !nGCS2
         #  AB20 & !AB21 & !AB22 & !BnOE & !IDE_DMARQ & !nGCS2;

-- Node name is 'DB4' 
-- Equation name is 'DB4', location is LC099, type is bidir.
DB4      = TRI(_LC099,  _LC035);
_LC099   = LCELL( EX_IN0 $  GND);

-- Node name is 'DB5' 
-- Equation name is 'DB5', location is LC097, type is bidir.
DB5      = TRI(_LC097,  _LC035);
_LC097   = LCELL( EX_IN1 $  GND);

-- Node name is 'DB6~1' 
-- Equation name is 'DB6~1', location is LC035, type is buried.
-- synthesized logic cell 
_LC035   = LCELL( _EQ018 $  GND);
  _EQ018 =  AB20 & !AB21 & !AB22 & !BnOE & !nGCS2;

-- Node name is 'DB6' 
-- Equation name is 'DB6', location is LC094, type is bidir.
DB6      = TRI(_LC094,  _LC035);
_LC094   = LCELL( EX_IN2 $  GND);

-- Node name is 'DB7' 
-- Equation name is 'DB7', location is LC093, type is bidir.
DB7      = TRI(_LC093,  _LC035);
_LC093   = LCELL( EX_IN2 $  GND);

-- Node name is 'EX_OUT0' = '|latch:281|OUT4' 
-- Equation name is 'EX_OUT0', type is output 
 EX_OUT0 = DFFE( DB3 $  GND,  _EQ019,  VCC,  VCC,  VCC);
  _EQ019 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'EX_OUT1' = '|latch:281|OUT5' 
-- Equation name is 'EX_OUT1', type is output 
 EX_OUT1 = DFFE( DB4 $  GND,  _EQ020,  VCC,  VCC,  VCC);
  _EQ020 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'EX_OUT2' = '|latch:281|OUT6' 
-- Equation name is 'EX_OUT2', type is output 
 EX_OUT2 = DFFE( DB5 $  GND,  _EQ021,  nUSB_EN,  VCC,  VCC);
  _EQ021 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'EXTBUS' 
-- Equation name is 'EXTBUS', location is LC070, type is output.
 EXTBUS  = LCELL( _EQ022 $  GND);
  _EQ022 =  nFRE &  nFWE &  nGCS1 &  nGCS2 &  nGCS3;

-- Node name is 'IDE_DMACK' = '|latch:281|OUT3' 
-- Equation name is 'IDE_DMACK', type is output 
 IDE_DMACK = DFFE( DB2 $  GND,  _EQ023,  VCC,  VCC,  VCC);
  _EQ023 = !AB20 & !AB21 & !AB22 & !BnWE & !nGCS2;

-- Node name is 'IDE_OE' 
-- Equation name is 'IDE_OE', location is LC027, type is output.
 IDE_OE  = LCELL( _EQ024 $  VCC);
  _EQ024 = !AB20 & !AB21 &  AB22 & !BnOE & !nGCS1;

-- Node name is 'IDE_WE' 
-- Equation name is 'IDE_WE', location is LC022, type is output.
 IDE_WE  = LCELL( _EQ025 $  VCC);
  _EQ025 = !AB20 & !AB21 &  AB22 & !BnWE & !nGCS1;

-- Node name is 'LCD_CD' 
-- Equation name is 'LCD_CD', location is LC125, type is output.
 LCD_CD  = LCELL( _EQ026 $  VCC);
  _EQ026 =  AB20 & !AB21 &  AB22 & !nGCS1;

-- Node name is 'NET_IOR' 
-- Equation name is 'NET_IOR', location is LC085, type is output.
 NET_IOR = LCELL( _EQ027 $  VCC);
  _EQ027 =  AB24 & !BnOE;

-- Node name is 'NET_IOW' 
-- Equation name is 'NET_IOW', location is LC081, type is output.
 NET_IOW = LCELL( _EQ028 $  VCC);
  _EQ028 =  AB24 & !BnWE;

-- Node name is 'NET_MEMR' 
-- Equation name is 'NET_MEMR', location is LC088, type is output.
 NET_MEMR = LCELL( _EQ029 $  VCC);
  _EQ029 = !AB24 & !BnOE & !nGCS3;

-- Node name is 'NET_MEMW' 
-- Equation name is 'NET_MEMW', location is LC089, type is output.
 NET_MEMW = LCELL( _EQ030 $  VCC);
  _EQ030 = !AB24 & !BnWE & !nGCS3;

-- Node name is 'nUSB_EN' = ':435' 
-- Equation name is 'nUSB_EN', type is output 
 nUSB_EN = LCELL( nRESET $  GND);

-- Node name is 'RESET' 
-- Equation name is 'RESET', location is LC078, type is output.
 RESET   = LCELL(!nRESET $  GND);

-- Node name is 'USB_CS' 
-- Equation name is 'USB_CS', location is LC075, type is output.
 USB_CS  = LCELL( _EQ031 $  VCC);
  _EQ031 = !AB20 & !AB21 & !AB22 & !nGCS1;

-- Node name is '1DIR' 
-- Equation name is '1DIR', location is LC073, type is output.
 1DIR    = LCELL( _EQ032 $  GND);
  _EQ032 =  nFRE &  nOE;

-- Node name is '2DIR' 
-- Equation name is '2DIR', location is LC072, type is output.
 2DIR    = LCELL( _EQ033 $  GND);
  _EQ033 =  nFRE &  nOE;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      e:\th\th1\edukit2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000AE' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,334K