📄 edukit2.rpt
字号:
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
25 33 C OUTPUT t 0 0 0 4 0 0 0 CAN_CS
8 25 B FF t 0 0 0 5 1 0 0 CF_CSEL (|latch:281|:2)
94 13 A OUTPUT t 0 0 0 4 0 0 0 CF_CS0
97 9 A OUTPUT t 0 0 0 4 0 0 0 CF_CS1
100 5 A OUTPUT t 0 0 0 5 0 0 0 CF_IORD
1 3 A OUTPUT t 0 0 0 5 0 0 0 CF_IOWR
98 8 A OUTPUT t 0 0 0 5 0 0 0 CF_MMRD
5 30 B OUTPUT t 0 0 0 5 0 0 0 CF_MMWR
12 21 B FF t 0 0 0 5 2 0 0 CF_WAIT (|latch:281|:1)
85 128 H OUTPUT t 0 0 0 1 0 0 0 CPLD_INT1
84 126 H OUTPUT t 0 0 0 4 0 0 0 CPLD_INT2
23 37 C OUTPUT t 0 0 0 5 0 0 0 CPLD_NFRE
21 40 C OUTPUT t 0 0 0 5 0 0 0 CPLD_NFWE
70 107 G TRI t 0 0 0 7 0 1 0 DB0
69 105 G TRI t 0 0 0 7 0 1 0 DB1
68 104 G TRI t 0 0 0 7 0 1 0 DB2
67 102 G TRI t 0 0 0 7 0 1 0 DB3
64 99 G TRI t 0 0 0 1 0 1 0 DB4
63 97 G TRI t 0 0 0 1 0 1 0 DB5
61 94 F TRI t 0 0 0 1 0 0 0 DB6
60 93 F TRI t 0 0 0 1 0 0 0 DB7
79 120 H FF t 0 0 0 5 1 0 0 EX_OUT0 (|latch:281|:4)
80 121 H FF t 0 0 0 5 1 0 0 EX_OUT1 (|latch:281|:5)
81 123 H FF t 0 0 0 5 2 0 0 EX_OUT2 (|latch:281|:6)
44 70 E OUTPUT t 0 0 0 5 0 0 0 EXTBUS
99 6 A FF t 0 0 0 5 1 0 0 IDE_DMACK (|latch:281|:3)
7 27 B OUTPUT t 0 0 0 5 0 0 0 IDE_OE
10 22 B OUTPUT t 0 0 0 5 0 0 0 IDE_WE
83 125 H OUTPUT t 0 0 0 4 0 0 0 LCD_CD
54 85 F OUTPUT t 0 0 0 2 0 0 0 NET_IOR
52 81 F OUTPUT t 0 0 0 2 0 0 0 NET_IOW
56 88 F OUTPUT t 0 0 0 3 0 0 0 NET_MEMR
57 89 F OUTPUT t 0 0 0 3 0 0 0 NET_MEMW
48 77 E OUTPUT t 0 0 0 1 0 2 0 nUSB_EN
49 78 E OUTPUT t 0 0 0 1 0 0 0 RESET
47 75 E OUTPUT t 0 0 0 4 0 0 0 USB_CS
46 73 E OUTPUT t 0 0 0 2 0 0 0 1DIR
45 72 E OUTPUT t 0 0 0 2 0 0 0 2DIR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(19) 43 C SOFT s t 2 0 0 5 0 0 0 DB2~1
(24) 35 C SOFT s t 0 0 0 5 0 0 0 DB6~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------- LC13 CF_CS0
| +--------- LC9 CF_CS1
| | +------- LC5 CF_IORD
| | | +----- LC3 CF_IOWR
| | | | +--- LC8 CF_MMRD
| | | | | +- LC6 IDE_DMACK
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'A'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
87 -> * * * * * * | * * * - * - * * | <-- AB20
88 -> * * * * * * | * * * - * - * * | <-- AB21
89 -> * * * * * * | * * * - * - * * | <-- AB22
41 -> - - * - * - | * * * - - * * - | <-- BnOE
42 -> - - - * - * | * * * - - * - * | <-- BnWE
31 -> * * - - - - | * * * - * - - * | <-- nGCS1
36 -> - - * * * * | * * * - * - * * | <-- nGCS2
90 -> - - - - - - | - - - - - - * - | <-- PS2_IO2
LC104-> - - - - - * | * - - - - - - - | <-- DB2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------- LC25 CF_CSEL
| +------- LC30 CF_MMWR
| | +----- LC21 CF_WAIT
| | | +--- LC27 IDE_OE
| | | | +- LC22 IDE_WE
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'B'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
87 -> * * * * * | * * * - * - * * | <-- AB20
88 -> * * * * * | * * * - * - * * | <-- AB21
89 -> * * * * * | * * * - * - * * | <-- AB22
41 -> - - - * - | * * * - - * * - | <-- BnOE
42 -> * * * - * | * * * - - * - * | <-- BnWE
31 -> - - - * * | * * * - * - - * | <-- nGCS1
36 -> * * * - - | * * * - * - * * | <-- nGCS2
90 -> - - - - - | - - - - - - * - | <-- PS2_IO2
LC107-> - - * - - | - * - - - - - - | <-- DB0
LC105-> * - - - - | - * - - - - - - | <-- DB1
LC77 -> - - * - - | - * - - - - - * | <-- nUSB_EN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------- LC33 CAN_CS
| +------- LC37 CPLD_NFRE
| | +----- LC40 CPLD_NFWE
| | | +--- LC43 DB2~1
| | | | +- LC35 DB6~1
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'C'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
87 -> * * * * * | * * * - * - * * | <-- AB20
88 -> * * * * * | * * * - * - * * | <-- AB21
89 -> * * * * * | * * * - * - * * | <-- AB22
41 -> - * - * * | * * * - - * * - | <-- BnOE
42 -> - - * - - | * * * - - * - * | <-- BnWE
31 -> * - - - - | * * * - * - - * | <-- nGCS1
36 -> - * * * * | * * * - * - * * | <-- nGCS2
90 -> - - - - - | - - - - - - * - | <-- PS2_IO2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+----------- LC70 EXTBUS
| +--------- LC77 nUSB_EN
| | +------- LC78 RESET
| | | +----- LC75 USB_CS
| | | | +--- LC73 1DIR
| | | | | +- LC72 2DIR
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'E'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
87 -> - - - * - - | * * * - * - * * | <-- AB20
88 -> - - - * - - | * * * - * - * * | <-- AB21
89 -> - - - * - - | * * * - * - * * | <-- AB22
22 -> * - - - * * | - - - - * - - - | <-- nFRE
20 -> * - - - - - | - - - - * - - - | <-- nFWE
31 -> * - - * - - | * * * - * - - * | <-- nGCS1
36 -> * - - - - - | * * * - * - * * | <-- nGCS2
32 -> * - - - - - | - - - - * * - - | <-- nGCS3
40 -> - - - - * * | - - - - * - - - | <-- nOE
9 -> - * * - - - | - - - - * - - - | <-- nRESET
90 -> - - - - - - | - - - - - - * - | <-- PS2_IO2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+----------- LC94 DB6
| +--------- LC93 DB7
| | +------- LC85 NET_IOR
| | | +----- LC81 NET_IOW
| | | | +--- LC88 NET_MEMR
| | | | | +- LC89 NET_MEMW
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'F'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
87 -> - - - - - - | * * * - * - * * | <-- AB20
88 -> - - - - - - | * * * - * - * * | <-- AB21
89 -> - - - - - - | * * * - * - * * | <-- AB22
71 -> - - * * * * | - - - - - * - - | <-- AB24
41 -> - - * - * - | * * * - - * * - | <-- BnOE
42 -> - - - * - * | * * * - - * - * | <-- BnWE
77 -> * * - - - - | - - - - - * - - | <-- EX_IN2
32 -> - - - - * * | - - - - * * - - | <-- nGCS3
90 -> - - - - - - | - - - - - - * - | <-- PS2_IO2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC107 DB0
| +--------- LC105 DB1
| | +------- LC104 DB2
| | | +----- LC102 DB3
| | | | +--- LC99 DB4
| | | | | +- LC97 DB5
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
87 -> * * * * - - | * * * - * - * * | <-- AB20
88 -> * * * * - - | * * * - * - * * | <-- AB21
89 -> * * * * - - | * * * - * - * * | <-- AB22
41 -> * * * * - - | * * * - - * * - | <-- BnOE
24 -> - - - * - - | - - - - - - * * | <-- CAN_INT
93 -> - * - - - - | - - - - - - * - | <-- CF_CD
6 -> * - - - - - | - - - - - - * * | <-- CF_INT
75 -> - - - - * - | - - - - - - * - | <-- EX_IN0
76 -> - - - - - * | - - - - - - * - | <-- EX_IN1
13 -> - - - * - - | - - - - - - * - | <-- IDE_DMARQ
96 -> - * - - - - | - - - - - - * * | <-- IDE_INT
2 -> - - * - - - | - - - - - - * - | <-- IDE_RDY
36 -> * * * * - - | * * * - * - * * | <-- nGCS2
92 -> - - * - - - | - - - - - - * * | <-- PS2_INT2
90 -> * - - - - - | - - - - - - * - | <-- PS2_IO2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------- LC128 CPLD_INT1
| +--------- LC126 CPLD_INT2
| | +------- LC120 EX_OUT0
| | | +----- LC121 EX_OUT1
| | | | +--- LC123 EX_OUT2
| | | | | +- LC125 LCD_CD
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'H'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
87 -> - - * * * * | * * * - * - * * | <-- AB20
88 -> - - * * * * | * * * - * - * * | <-- AB21
89 -> - - * * * * | * * * - * - * * | <-- AB22
42 -> - - * * * - | * * * - - * - * | <-- BnWE
24 -> - * - - - - | - - - - - - * * | <-- CAN_INT
6 -> - * - - - - | - - - - - - * * | <-- CF_INT
96 -> - * - - - - | - - - - - - * * | <-- IDE_INT
31 -> - - - - - * | * * * - * - - * | <-- nGCS1
36 -> - - * * * - | * * * - * - * * | <-- nGCS2
92 -> - * - - - - | - - - - - - * * | <-- PS2_INT2
90 -> - - - - - - | - - - - - - * - | <-- PS2_IO2
27 -> * - - - - - | - - - - - - - * | <-- TSP_INT
LC102-> - - * - - - | - - - - - - - * | <-- DB3
LC99 -> - - - * - - | - - - - - - - * | <-- DB4
LC97 -> - - - - * - | - - - - - - - * | <-- DB5
LC77 -> - - - - * - | - * - - - - - * | <-- nUSB_EN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\th\th1\edukit2.rpt
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