📄 edukit2.rpt
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Project Information e:\th\th1\edukit2.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 10/09/2005 17:15:58
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
edukit2 EPM7128AETC100-5 37 30 8 40 2 31 %
User Pins: 37 30 8
Project Information e:\th\th1\edukit2.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'AB2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'AB3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'NFCE' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'PS2_INT1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'GPB10' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'AB23' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'AB0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'AB1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'GPB9' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'nWAIT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'CLKPUT0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'nGCS4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information e:\th\th1\edukit2.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
edukit2@19 AB0
edukit2@14 AB1
edukit2@16 AB2
edukit2@17 AB3
edukit2@87 AB20
edukit2@88 AB21
edukit2@89 AB22
edukit2@58 AB23
edukit2@71 AB24
edukit2@41 BnOE
edukit2@42 BnWE
edukit2@25 CAN_CS
edukit2@24 CAN_INT
edukit2@93 CF_CD
edukit2@8 CF_CSEL
edukit2@94 CF_CS0
edukit2@97 CF_CS1
edukit2@6 CF_INT
edukit2@100 CF_IORD
edukit2@1 CF_IOWR
edukit2@98 CF_MMRD
edukit2@5 CF_MMWR
edukit2@12 CF_WAIT
edukit2@30 CLKPUT0
edukit2@85 CPLD_INT1
edukit2@84 CPLD_INT2
edukit2@23 CPLD_NFRE
edukit2@21 CPLD_NFWE
edukit2@70 DB0
edukit2@69 DB1
edukit2@68 DB2
edukit2@67 DB3
edukit2@64 DB4
edukit2@63 DB5
edukit2@61 DB6
edukit2@60 DB7
edukit2@75 EX_IN0
edukit2@76 EX_IN1
edukit2@77 EX_IN2
edukit2@79 EX_OUT0
edukit2@80 EX_OUT1
edukit2@81 EX_OUT2
edukit2@44 EXTBUS
edukit2@28 GPB9
edukit2@29 GPB10
edukit2@99 IDE_DMACK
edukit2@13 IDE_DMARQ
edukit2@96 IDE_INT
edukit2@7 IDE_OE
edukit2@2 IDE_RDY
edukit2@10 IDE_WE
edukit2@83 LCD_CD
edukit2@54 NET_IOR
edukit2@52 NET_IOW
edukit2@56 NET_MEMR
edukit2@57 NET_MEMW
edukit2@35 NFCE
edukit2@22 nFRE
edukit2@20 nFWE
edukit2@31 nGCS1
edukit2@36 nGCS2
edukit2@32 nGCS3
edukit2@37 nGCS4
edukit2@40 nOE
edukit2@9 nRESET
edukit2@48 nUSB_EN
edukit2@50 nWAIT
edukit2@72 PS2_INT1
edukit2@92 PS2_INT2
edukit2@90 PS2_IO2
edukit2@49 RESET
edukit2@27 TSP_INT
edukit2@47 USB_CS
edukit2@46 1DIR
edukit2@45 2DIR
Project Information e:\th\th1\edukit2.rpt
** FILE HIERARCHY **
|74138:194|
|74138:177|
|latch:281|
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
***** Logic for device 'edukit2' compiled without errors.
Device: EPM7128AETC100-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** ERROR SUMMARY **
Info: Chip 'edukit2' in device 'EPM7128AETC100-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
I C C
D P P P
C E C I S P L L E E E
F _ F C D C 2 V S D D L X X X E E
_ D _ F E F C _ C 2 _ _ C V _ _ _ X X
I M M _ _ _ F I C _ A A A I I D C O O O G _ _
O A M C I G C _ N I I B B B G N N _ C U U U N I I
R C R S N N S C T N O 2 2 2 N T T C I T T T D N N
D K D 1 T D 0 D 2 T 2 2 1 0 D 1 2 D O 2 1 0 * 2 1
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
CF_IOWR | 1 75 | EX_IN0
IDE_RDY | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | PS2_INT1
CF_MMWR | 5 71 | AB24
CF_INT | 6 70 | DB0
IDE_OE | 7 69 | DB1
CF_CSEL | 8 68 | DB2
nRESET | 9 67 | DB3
IDE_WE | 10 66 | VCCIO
GND | 11 65 | GND*
CF_WAIT | 12 64 | DB4
IDE_DMARQ | 13 EPM7128AETC100-5 63 | DB5
AB1 | 14 62 | #TCK
#TMS | 15 61 | DB6
AB2 | 16 60 | DB7
AB3 | 17 59 | GND
VCCIO | 18 58 | AB23
AB0 | 19 57 | NET_MEMW
nFWE | 20 56 | NET_MEMR
CPLD_NFWE | 21 55 | GND*
nFRE | 22 54 | NET_IOR
CPLD_NFRE | 23 53 | GND*
CAN_INT | 24 52 | NET_IOW
CAN_CS | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G T G G C n n G V N n n G V n B B G E 2 1 U n R n
N S P P L G G N C F G G N C O n n N X D D S U E W
D P B B K C C D C C C C D C E O W D T I I B S S A
_ 9 1 P S S * I E S S I E E B R R _ B E I
I 0 U 1 3 O 2 4 N U C _ T T
N T T S S E
T 0 N
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 6/16( 37%) 10/10(100%) 0/16( 0%) 8/36( 22%)
B: LC17 - LC32 5/16( 31%) 10/10(100%) 0/16( 0%) 10/36( 27%)
C: LC33 - LC48 5/16( 31%) 10/10(100%) 2/16( 12%) 7/36( 19%)
D: LC49 - LC64 0/16( 0%) 9/10( 90%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 6/16( 37%) 10/10(100%) 0/16( 0%) 10/36( 27%)
F: LC81 - LC96 6/16( 37%) 8/10( 80%) 0/16( 0%) 5/36( 13%)
G: LC97 - LC112 6/16( 37%) 9/10( 90%) 0/16( 0%) 15/36( 41%)
H: LC113 - LC128 6/16( 37%) 9/10( 90%) 0/16( 0%) 15/36( 41%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 75/80 ( 93%)
Total logic cells used: 40/128 ( 31%)
Total shareable expanders used: 2/128 ( 1%)
Total Turbo logic cells used: 40/128 ( 31%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 4.35
Total fan-in: 174
Total input pins required: 37
Total fast input logic cells required: 0
Total output pins required: 30
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 40
Total flipflops required: 6
Total product terms required: 54
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 2/ 128 ( 1%)
Device-Specific Information: e:\th\th1\edukit2.rpt
edukit2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
19 (43) (C) INPUT 0 0 0 0 0 0 0 AB0
14 (17) (B) INPUT 0 0 0 0 0 0 0 AB1
16 (46) (C) INPUT 0 0 0 0 0 0 0 AB2
17 (45) (C) INPUT 0 0 0 0 0 0 0 AB3
87 - - INPUT 0 0 0 0 0 23 2 AB20
88 - - INPUT 0 0 0 0 0 23 2 AB21
89 - - INPUT 0 0 0 0 0 23 2 AB22
58 (91) (F) INPUT 0 0 0 0 0 0 0 AB23
71 (109) (G) INPUT 0 0 0 0 0 4 0 AB24
41 (67) (E) INPUT 0 0 0 0 0 10 2 BnOE
42 (69) (E) INPUT 0 0 0 0 0 12 0 BnWE
24 (35) (C) INPUT 0 0 0 0 0 2 0 CAN_INT
93 (14) (A) INPUT 0 0 0 0 0 1 0 CF_CD
6 (29) (B) INPUT 0 0 0 0 0 2 0 CF_INT
30 (59) (D) INPUT 0 0 0 0 0 0 0 CLKPUT0
70 107 G BIDIR 0 0 0 7 0 1 0 DB0
69 105 G BIDIR 0 0 0 7 0 1 0 DB1
68 104 G BIDIR 0 0 0 7 0 1 0 DB2
67 102 G BIDIR 0 0 0 7 0 1 0 DB3
64 99 G BIDIR 0 0 0 1 0 1 0 DB4
63 97 G BIDIR 0 0 0 1 0 1 0 DB5
61 94 F BIDIR 0 0 0 1 0 0 0 DB6
60 93 F BIDIR 0 0 0 1 0 0 0 DB7
75 (113) (H) INPUT 0 0 0 0 0 1 0 EX_IN0
76 (115) (H) INPUT 0 0 0 0 0 1 0 EX_IN1
77 (117) (H) INPUT 0 0 0 0 0 2 0 EX_IN2
28 (62) (D) INPUT 0 0 0 0 0 0 0 GPB9
29 (61) (D) INPUT 0 0 0 0 0 0 0 GPB10
13 (19) (B) INPUT 0 0 0 0 0 1 0 IDE_DMARQ
96 (11) (A) INPUT 0 0 0 0 0 2 0 IDE_INT
2 (1) (A) INPUT 0 0 0 0 0 1 0 IDE_RDY
35 (53) (D) INPUT 0 0 0 0 0 0 0 NFCE
22 (38) (C) INPUT 0 0 0 0 0 3 0 nFRE
20 (41) (C) INPUT 0 0 0 0 0 1 0 nFWE
31 (57) (D) INPUT 0 0 0 0 0 8 0 nGCS1
36 (51) (D) INPUT 0 0 0 0 0 17 2 nGCS2
32 (56) (D) INPUT 0 0 0 0 0 3 0 nGCS3
37 (49) (D) INPUT 0 0 0 0 0 0 0 nGCS4
40 (65) (E) INPUT 0 0 0 0 0 2 0 nOE
9 (24) (B) INPUT 0 0 0 0 0 2 0 nRESET
50 (80) (E) INPUT 0 0 0 0 0 0 0 nWAIT
72 (110) (G) INPUT 0 0 0 0 0 0 0 PS2_INT1
92 (16) (A) INPUT 0 0 0 0 0 2 0 PS2_INT2
90 - - INPUT 0 0 0 0 0 1 0 PS2_IO2
27 (64) (D) INPUT 0 0 0 0 0 1 0 TSP_INT
Code:
s = Synthesized pin or logic cell
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