pmc5382_rx_pl3.v

VERILOG五POSPHY LEVEL3电路描述

                                                                                                                              
                       //test signals
                       test_sel,
                       test_point                 
                       );
                       
                       
//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;
                     
//signals from pmc5382 block
output pmc5382_renb;
input  pmc5382_rsx;                       
input  pmc5382_rval;

input [31:0]pmc5382_rdat;                      
input       pmc5382_rsop;
input       pmc5382_reop;
input  [1:0]pmc5382_rmod;
input       pmc5382_rerr;
input       pmc5382_rprty;
                                                                                                                                                                                                       
//signals to pmc3386_tx_pl3 block 
output ch0_fifo_aval;
output ch1_fifo_aval;
output ch2_fifo_aval;
output ch3_fifo_aval;
output ch4_fifo_aval;
output ch5_fifo_aval;
output ch6_fifo_aval;
output ch7_fifo_aval;
output ch8_fifo_aval;
output ch9_fifo_aval;
output ch10_fifo_aval;
output ch11_fifo_aval;
output ch12_fifo_aval;         
output ch13_fifo_aval;
output ch14_fifo_aval;
output ch15_fifo_aval;

input ch0_fifo_rden;
input ch1_fifo_rden;
input ch2_fifo_rden;
input ch3_fifo_rden;
input ch4_fifo_rden;
input ch5_fifo_rden;
input ch6_fifo_rden;
input ch7_fifo_rden;
input ch8_fifo_rden;
input ch9_fifo_rden;
input ch10_fifo_rden;
input ch11_fifo_rden;
input ch12_fifo_rden;
input ch13_fifo_rden;
input ch14_fifo_rden;
input ch15_fifo_rden;

//ch0
output [31:0]ch0_fifo_data;
output       ch0_fifo_sop;
output       ch0_fifo_eop;
output  [1:0]ch0_fifo_mod;
output       ch0_fifo_err;
output       ch0_fifo_par; 
//ch1
output [31:0]ch1_fifo_data;
output       ch1_fifo_sop;
output       ch1_fifo_eop;
output  [1:0]ch1_fifo_mod;
output       ch1_fifo_err; 
output       ch1_fifo_par;
//ch2
output [31:0]ch2_fifo_data;
output       ch2_fifo_sop;
output       ch2_fifo_eop;
output  [1:0]ch2_fifo_mod;
output       ch2_fifo_err; 
output       ch2_fifo_par;
//ch3
output [31:0]ch3_fifo_data;
output       ch3_fifo_sop;
output       ch3_fifo_eop;
output  [1:0]ch3_fifo_mod;
output       ch3_fifo_err; 
output       ch3_fifo_par;
//ch4
output [31:0]ch4_fifo_data;
output       ch4_fifo_sop;
output       ch4_fifo_eop;
output  [1:0]ch4_fifo_mod;
output       ch4_fifo_err; 
output       ch4_fifo_par;
//ch5
output [31:0]ch5_fifo_data;
output       ch5_fifo_sop;
output       ch5_fifo_eop;
output  [1:0]ch5_fifo_mod;
output       ch5_fifo_err; 
output       ch5_fifo_par;
//ch6
output [31:0]ch6_fifo_data;
output       ch6_fifo_sop;
output       ch6_fifo_eop;
output  [1:0]ch6_fifo_mod;
output       ch6_fifo_err; 
output       ch6_fifo_par;
//ch7
output [31:0]ch7_fifo_data;
output       ch7_fifo_sop;
output       ch7_fifo_eop;
output  [1:0]ch7_fifo_mod;
output       ch7_fifo_err; 
output       ch7_fifo_par;
//ch8
output [31:0]ch8_fifo_data;
output       ch8_fifo_sop;
output       ch8_fifo_eop;
output  [1:0]ch8_fifo_mod;
output       ch8_fifo_err; 
output       ch8_fifo_par;
//ch9
output [31:0]ch9_fifo_data;
output       ch9_fifo_sop;
output       ch9_fifo_eop;
output  [1:0]ch9_fifo_mod;
output       ch9_fifo_err; 
output       ch9_fifo_par;
//ch10
output [31:0]ch10_fifo_data;
output       ch10_fifo_sop;
output       ch10_fifo_eop;
output  [1:0]ch10_fifo_mod;
output       ch10_fifo_err; 
output       ch10_fifo_par;
//ch11
output [31:0]ch11_fifo_data;
output       ch11_fifo_sop;
output       ch11_fifo_eop;
output  [1:0]ch11_fifo_mod;
output       ch11_fifo_err; 
output       ch11_fifo_par;
//ch12
output [31:0]ch12_fifo_data;
output       ch12_fifo_sop;
output       ch12_fifo_eop;
output  [1:0]ch12_fifo_mod;
output       ch12_fifo_err; 
output       ch12_fifo_par;
//ch13
output [31:0]ch13_fifo_data;
output       ch13_fifo_sop;
output       ch13_fifo_eop;
output  [1:0]ch13_fifo_mod;
output       ch13_fifo_err; 
output       ch13_fifo_par;
//ch14
output [31:0]ch14_fifo_data;
output       ch14_fifo_sop;
output       ch14_fifo_eop;
output  [1:0]ch14_fifo_mod;
output       ch14_fifo_err; 
output       ch14_fifo_par;
//ch15
output [31:0]ch15_fifo_data;
output       ch15_fifo_sop;
output       ch15_fifo_eop;
output  [1:0]ch15_fifo_mod;
output       ch15_fifo_err; 
output       ch15_fifo_par;
                       
//signals from m_bus block
input header_length;
input crc_length;
input [47:0]ge0_da_mac;
input [47:0]ge0_sa_mac;
input [47:0]ge1_da_mac;
input [47:0]ge1_sa_mac;
input [47:0]ge2_da_mac;
input [47:0]ge2_sa_mac;
input [47:0]ge3_da_mac;
input [47:0]ge3_sa_mac;

output [15:0]lose_pkt_cnt_0;
output [15:0]lose_pkt_cnt_1;
output [15:0]lose_pkt_cnt_2;
output [15:0]lose_pkt_cnt_3;
output [15:0]lose_pkt_cnt_4;
output [15:0]lose_pkt_cnt_5;
output [15:0]lose_pkt_cnt_6;
output [15:0]lose_pkt_cnt_7;
output [15:0]lose_pkt_cnt_8;
output [15:0]lose_pkt_cnt_9;
output [15:0]lose_pkt_cnt_10;
output [15:0]lose_pkt_cnt_11;
output [15:0]lose_pkt_cnt_12;
output [15:0]lose_pkt_cnt_13;
output [15:0]lose_pkt_cnt_14;
output [15:0]lose_pkt_cnt_15;
                                                                                                                             
//test signals
input   [7:0]test_sel;
output [31:0]test_point;

///////////
reg  pmc5382_renb;

reg [31:0]test_point;

////////////////////////////////////////////////////////////////////////////////////////
//internal reg
reg  [3:0]ch_id;

reg wren_sop_tmp0,wren_sop_tmp1,wren_sop_tmp2,wren_sop_tmp3,wren_sop_tmp4,wren_sop_tmp5,wren_sop_tmp6,wren_sop_tmp7,
    wren_sop_tmp8,wren_sop_tmp9,wren_sop_tmp10,wren_sop_tmp11,wren_sop_tmp12,wren_sop_tmp13,wren_sop_tmp14,wren_sop_tmp15;
    
reg wren_eop_tmp0,wren_eop_tmp1,wren_eop_tmp2,wren_eop_tmp3,wren_eop_tmp4,wren_eop_tmp5,wren_eop_tmp6,wren_eop_tmp7,
    wren_eop_tmp8,wren_eop_tmp9,wren_eop_tmp10,wren_eop_tmp11,wren_eop_tmp12,wren_eop_tmp13,wren_eop_tmp14,wren_eop_tmp15;
    
reg wren_err_tmp0,wren_err_tmp1,wren_err_tmp2,wren_err_tmp3,wren_err_tmp4,wren_err_tmp5,wren_err_tmp6,wren_err_tmp7,
    wren_err_tmp8,wren_err_tmp9,wren_err_tmp10,wren_err_tmp11,wren_err_tmp12,wren_err_tmp13,wren_err_tmp14,wren_err_tmp15;
    
reg [1:0]wren_mod_tmp0,wren_mod_tmp1,wren_mod_tmp2,wren_mod_tmp3,wren_mod_tmp4,wren_mod_tmp5,wren_mod_tmp6,wren_mod_tmp7,
         wren_mod_tmp8,wren_mod_tmp9,wren_mod_tmp10,wren_mod_tmp11,wren_mod_tmp12,wren_mod_tmp13,wren_mod_tmp14,wren_mod_tmp15;
         
reg [31:0]wren_data_tmp0,wren_data_tmp1,wren_data_tmp2,wren_data_tmp3,wren_data_tmp4,wren_data_tmp5,wren_data_tmp6,wren_data_tmp7,
          wren_data_tmp8,wren_data_tmp9,wren_data_tmp10,wren_data_tmp11,wren_data_tmp12,wren_data_tmp13,wren_data_tmp14,wren_data_tmp15;
          
reg wren_val_tmp0,wren_val_tmp1,wren_val_tmp2,wren_val_tmp3,wren_val_tmp4,wren_val_tmp5,wren_val_tmp6,wren_val_tmp7,