pmc5382_rx_pl3.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : pmc5382_rx_pl3.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pmc5382_to_pmc3386_pl3.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module pmc5382_rx_pl3(
                       //system signals
                       h_reset_n,
                       s_reset_n,
                       sys_clk_100m,
                                             
                       //signals from pmc5382 block
                       pmc5382_renb,
                       pmc5382_rsx,                       
                       pmc5382_rval,
                       
                       pmc5382_rdat,                      
                       pmc5382_rsop,
                       pmc5382_reop,
                       pmc5382_rmod,
                       pmc5382_rerr,
                       pmc5382_rprty,
                                                                                                                                                                                                                              
                       //signals to pmc3386_tx_pl3 block 
                       ch0_fifo_aval,
                       ch1_fifo_aval,
                       ch2_fifo_aval,
                       ch3_fifo_aval,
                       ch4_fifo_aval,
                       ch5_fifo_aval,
                       ch6_fifo_aval,
                       ch7_fifo_aval,
                       ch8_fifo_aval,
                       ch9_fifo_aval,
                       ch10_fifo_aval,
                       ch11_fifo_aval,
                       ch12_fifo_aval,         
                       ch13_fifo_aval,
                       ch14_fifo_aval,
                       ch15_fifo_aval,
                                                                     
                       ch0_fifo_rden,
                       ch1_fifo_rden,
                       ch2_fifo_rden,
                       ch3_fifo_rden,
                       ch4_fifo_rden,
                       ch5_fifo_rden,
                       ch6_fifo_rden,
                       ch7_fifo_rden,
                       ch8_fifo_rden,
                       ch9_fifo_rden,
                       ch10_fifo_rden,
                       ch11_fifo_rden,
                       ch12_fifo_rden,
                       ch13_fifo_rden,
                       ch14_fifo_rden,
                       ch15_fifo_rden,
                       
                       //ch0
                       ch0_fifo_data,
                       ch0_fifo_sop,
                       ch0_fifo_eop,
                       ch0_fifo_mod,
                       ch0_fifo_err, 
                       ch0_fifo_par,
                       //ch1
                       ch1_fifo_data,
                       ch1_fifo_sop,
                       ch1_fifo_eop,
                       ch1_fifo_mod,
                       ch1_fifo_err, 
                       ch1_fifo_par,
                       //ch2
                       ch2_fifo_data,
                       ch2_fifo_sop,
                       ch2_fifo_eop,
                       ch2_fifo_mod,
                       ch2_fifo_err, 
                       ch2_fifo_par,
                       //ch3
                       ch3_fifo_data,
                       ch3_fifo_sop,
                       ch3_fifo_eop,
                       ch3_fifo_mod,
                       ch3_fifo_err, 
                       ch3_fifo_par,
                       //ch4
                       ch4_fifo_data,
                       ch4_fifo_sop,
                       ch4_fifo_eop,
                       ch4_fifo_mod,
                       ch4_fifo_err, 
                       ch4_fifo_par,
                       //ch5
                       ch5_fifo_data,
                       ch5_fifo_sop,
                       ch5_fifo_eop,
                       ch5_fifo_mod,
                       ch5_fifo_err, 
                       ch5_fifo_par,
                       //ch6
                       ch6_fifo_data,
                       ch6_fifo_sop,
                       ch6_fifo_eop,
                       ch6_fifo_mod,
                       ch6_fifo_err, 
                       ch6_fifo_par,
                       //ch7
                       ch7_fifo_data,
                       ch7_fifo_sop,
                       ch7_fifo_eop,
                       ch7_fifo_mod,
                       ch7_fifo_err, 
                       ch7_fifo_par,
                       //ch8
                       ch8_fifo_data,
                       ch8_fifo_sop,
                       ch8_fifo_eop,
                       ch8_fifo_mod,
                       ch8_fifo_err, 
                       ch8_fifo_par,
                       //ch9
                       ch9_fifo_data,
                       ch9_fifo_sop,
                       ch9_fifo_eop,
                       ch9_fifo_mod,
                       ch9_fifo_err, 
                       ch9_fifo_par,
                       //ch10
                       ch10_fifo_data,
                       ch10_fifo_sop,
                       ch10_fifo_eop,
                       ch10_fifo_mod,
                       ch10_fifo_err, 
                       ch10_fifo_par,
                       //ch11
                       ch11_fifo_data,
                       ch11_fifo_sop,
                       ch11_fifo_eop,
                       ch11_fifo_mod,
                       ch11_fifo_err, 
                       ch11_fifo_par,
                       //ch12
                       ch12_fifo_data,
                       ch12_fifo_sop,
                       ch12_fifo_eop,
                       ch12_fifo_mod,
                       ch12_fifo_err, 
                       ch12_fifo_par,
                       //ch13
                       ch13_fifo_data,
                       ch13_fifo_sop,
                       ch13_fifo_eop,
                       ch13_fifo_mod,
                       ch13_fifo_err, 
                       ch13_fifo_par,
                       //ch14
                       ch14_fifo_data,
                       ch14_fifo_sop,
                       ch14_fifo_eop,
                       ch14_fifo_mod,
                       ch14_fifo_err, 
                       ch14_fifo_par,
                       //ch15
                       ch15_fifo_data,
                       ch15_fifo_sop,
                       ch15_fifo_eop,
                       ch15_fifo_mod,
                       ch15_fifo_err, 
                       ch15_fifo_par,
                                              
                       //signals from m_bus block
                       header_length,
                       crc_length,
                       
                       ge0_da_mac,
                       ge0_sa_mac,
                       ge1_da_mac,
                       ge1_sa_mac,
                       ge2_da_mac,
                       ge2_sa_mac,
                       ge3_da_mac,
                       ge3_sa_mac,
                       
                       lose_pkt_cnt_0,
                       lose_pkt_cnt_1,
                       lose_pkt_cnt_2,
                       lose_pkt_cnt_3,
                       lose_pkt_cnt_4,
                       lose_pkt_cnt_5,
                       lose_pkt_cnt_6,
                       lose_pkt_cnt_7,
                       lose_pkt_cnt_8,
                       lose_pkt_cnt_9,
                       lose_pkt_cnt_10,
                       lose_pkt_cnt_11,
                       lose_pkt_cnt_12,
                       lose_pkt_cnt_13,
                       lose_pkt_cnt_14,
                       lose_pkt_cnt_15,