rx_pkt_ram_pro.v

VERILOG五POSPHY LEVEL3电路描述

      wren_err <=1'b0;
      wren_mod <=2'b0; 
    end
  else if(wren_eop_tmp_2d)
    begin
      case(wren_mod_tmp_2d[1:0])
        2'b00: begin wren_eop <=1'b0; 
                     wren_err <=1'b0; 
                     wren_mod <=2'b10; 
               end
        2'b01: begin wren_eop <=1'b0; 
                     wren_err <=1'b0; 
                     wren_mod <=2'b11; 
               end 
        2'b10: begin wren_eop <=wren_eop_tmp_2d; 
                     wren_err <=wren_err_tmp_2d; 
                     wren_mod <=2'b00; 
               end 
        2'b11: begin wren_eop <=wren_eop_tmp_2d; 
                     wren_err <=wren_err_tmp_2d; 
                     wren_mod <=2'b01;
               end 
        default: ;
      endcase
    end
  else if(wren_eop_tmp_3d)
    begin
      case(wren_mod_tmp_3d[1:0])
        2'b00: begin wren_eop <=wren_eop_tmp_3d; 
                     wren_err <=wren_err_tmp_3d; 
                     wren_mod <=2'b10; 
               end  
        2'b01: begin wren_eop <=wren_eop_tmp_3d; 
                     wren_err <=wren_err_tmp_3d; 
                     wren_mod <=2'b11; 
               end 
        2'b10: begin wren_eop <=1'b0; 
                     wren_err <=1'b0; 
                     wren_mod <=2'b00; 
               end  
        2'b11: begin wren_eop <=1'b0; 
                     wren_err <=1'b0; 
                     wren_mod <=2'b10; 
               end
        default: ;
      endcase
    end
  else
    begin
      wren_eop <=1'b0;
      wren_err <=1'b0; 
      wren_mod <=2'b0;
    end
end

//wren_data
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_data[31:0] <=32'b0;
    end
  else if(~s_reset_n)
    begin
      wren_data[31:0] <=32'b0;
    end
  else if(wren_sop_tmp)
    begin
      wren_data[31:0] <={ge_da_mac[7:0],ge_da_mac[15:8],ge_da_mac[23:16],ge_da_mac[31:24]};      
    end
  else if(wren_sop)
    begin
      wren_data[31:0] <={ge_da_mac[39:32],ge_da_mac[47:40],ge_sa_mac[7:0],ge_sa_mac[15:8]};      
    end  
  else if(wren_sop_d)
    begin
      wren_data[31:0] <={ge_sa_mac[23:16],ge_sa_mac[31:24],ge_sa_mac[39:32],ge_sa_mac[47:40]}; 
    end
  else if(wren_sop_2d)
    begin
      wren_data[31:0] <={16'h0800,wren_data_tmp_2d[31:16]}; 
    end
  //else if(~wren_val_tmp_2d && wren_val_tmp_3d)
  //  begin
  //    wren_data[31:0] <={wren_data_tmp_3d[15:0],wren_data_tmp_d[31:16]}; 
  //  end
  //else if(wren_val_tmp_2d && ~wren_val_tmp_3d)
  //  begin
  //    wren_data[31:0] <=32'b0;
  //  end  
//  else if(wren_sop_3d)
//    begin
//      wren_data[31:0] <={wren_data_tmp_3d[15:0],wren_data_tmp_2d[31:16]}; 
//    end    
  else
    begin
      wren_data[31:0] <={wren_data_tmp_3d[15:0],wren_data_tmp_2d[31:16]};
    end
end

//wren_par
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_par <=1'b0;       
    end
  else if(~s_reset_n)
    begin
      wren_par <=1'b0; 
    end
  else
    begin
      wren_par <=1'b0; 
    end
end

//wr_pkt_unfinished_tmp
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wr_pkt_unfinished_tmp <=1'b0;   
    end
  else if(~s_reset_n)
    begin
      wr_pkt_unfinished_tmp <=1'b0; 
    end
  else if(wren_sop_tmp)
    begin
      wr_pkt_unfinished_tmp <=1'b1;  
    end
  else if(wren_eop)
    begin
      wr_pkt_unfinished_tmp <=1'b0;  
    end
  else
    begin
      wr_pkt_unfinished_tmp <=wr_pkt_unfinished_tmp;
    end
end

//wr_ram_en
assign wr_ram_en = wr_pkt_unfinished_tmp && (wren_sop_tmp||wren_sop_tmp_d||wren_sop_tmp_2d||wren_sop_tmp_3d||wren_val_tmp_3d || wren_eop);

//wr_ram1,2_dq
assign wr_ram1_dq[35:0] = {wren_sop,wren_eop,wren_mod[1:0],wren_data[31:0]};
assign wr_ram2_dq[1:0]  = {wren_err,wren_par};

//packet_start_addx
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    packet_start_addx<=10'b0;
  else if(~s_reset_n)
    packet_start_addx<=10'b0;
  else if(wr_ram_en && wren_sop)
    packet_start_addx<=wr_ram_addx;
end

//wr_ram_addx
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wr_ram_addx<=10'h0;
    end
  else if(~s_reset_n)
    begin
      wr_ram_addx<=10'h0;
    end
  else if(wr_ram_en)
    begin
      if(rx_pkt_ram_full || rx_pkt_ram_full_tmp)    
        wr_ram_addx<=packet_start_addx;
      else
        wr_ram_addx<=wr_ram_addx + 10'h1;      
    end    
  else
    begin
      wr_ram_addx<=wr_ram_addx;
    end
end

//rx_pkt_ram_full
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rx_pkt_ram_full<=1'b0;
    end
  else if(~s_reset_n)
    begin
      rx_pkt_ram_full<=1'b0;
    end
  else if(ch_fifo_eop||ch_fifo_eop_d||ch_fifo_eop_2d)
    rx_pkt_ram_full<=1'b0; 
  else if(((wr_ram_addx>=rd_ram_addx)&&(10'd1023-wr_ram_addx+rd_ram_addx<=10'd2))||
          ((wr_ram_addx<rd_ram_addx)&&(rd_ram_addx-wr_ram_addx<=10'd2)))
    begin
      rx_pkt_ram_full<=1'b1;
    end
  else
    begin
      rx_pkt_ram_full<=1'b0;
    end
end

//rx_pkt_ram_full_tmp
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rx_pkt_ram_full_tmp<=1'b0;
    end
  else if(~s_reset_n)
    begin
      rx_pkt_ram_full_tmp<=1'b0;
    end
  else if(wr_pkt_unfinished_tmp)
    begin
      if(rx_pkt_ram_full)
        rx_pkt_ram_full_tmp<=1'b1;
      else 
        rx_pkt_ram_full_tmp<=rx_pkt_ram_full_tmp; 
    end
  else
    begin
      rx_pkt_ram_full_tmp<=1'b0;
    end
end

//rx_pkt_ram1024x38
rx_pkt_ram1024x36  rx_pkt_ram1024x36 (
	           .data(wr_ram1_dq),
	           .wren(wr_ram_en),
	           .wraddress(wr_ram_addx),
	           .rdaddress(rd_ram_addx),
	           .rden(ch_fifo_rden),
	           .clock(sys_clk_100m),
	           .q(rd_ram1_dq)
	           );

rx_pkt_ram1024x2  rx_pkt_ram1024x2 (
	           .data(wr_ram2_dq),
	           .wren(wr_ram_en),
	           .wraddress(wr_ram_addx),
	           .rdaddress(rd_ram_addx),
	           .rden(ch_fifo_rden),
	           .clock(sys_clk_100m),
	           .q(rd_ram2_dq)
	           );
	           
//rcv_pkt_cnt
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rcv_pkt_cnt[7:0] <=8'd0;   
    end
  else if(~s_reset_n)
    begin
      rcv_pkt_cnt[7:0] <=8'd0;
    end
  else if((wr_ram_en && wren_eop && ~(rx_pkt_ram_full || rx_pkt_ram_full_tmp))
        &&(ch_fifo_rden && ch_fifo_eop))
    begin
      rcv_pkt_cnt[7:0] <=rcv_pkt_cnt[7:0];
    end 
  else if(wr_ram_en && wren_eop && ~(rx_pkt_ram_full || rx_pkt_ram_full_tmp))
    begin
      rcv_pkt_cnt[7:0] <=rcv_pkt_cnt[7:0]+8'd1;
    end
  else if(ch_fifo_rden && ch_fifo_eop)
    begin
      rcv_pkt_cnt[7:0] <=rcv_pkt_cnt[7:0]-8'd1;
    end
  else
    begin
      rcv_pkt_cnt <=rcv_pkt_cnt; 
    end
end

//ch_fifo_aval
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      ch_fifo_aval <=1'b0;   
    end
  else if(~s_reset_n)
    begin
      ch_fifo_aval <=1'b0;
    end
  else if(rcv_pkt_cnt[7:0]>=8'd1)
    begin
      ch_fifo_aval <=1'b1;
    end 
  else
    begin
      ch_fifo_aval <=1'b0;
    end
end

wire [35:0]rd_ram1_dq_tmp;
wire [1:0] rd_ram2_dq_tmp;
 
assign rd_ram1_dq_tmp = (ch_fifo_rden && ch_fifo_rden_2d) ? rd_ram1_dq : 36'b0; 
assign rd_ram2_dq_tmp = (ch_fifo_rden && ch_fifo_rden_2d) ? rd_ram2_dq : 2'b0;

//rd_ram_addx
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rd_ram_addx<=10'h0;
    end
  else if(~s_reset_n)
    begin
      rd_ram_addx<=10'h0;
    end  
  else if(ch_fifo_rden) //&& ~rd_ram1_dq_tmp[34])
    begin     
      rd_ram_addx<=rd_ram_addx + 10'h1;
    end
  else if(!ch_fifo_rden && ch_fifo_rden_2d)
    begin
      rd_ram_addx<=rd_ram_addx - 10'h1;
    end
  else 
    begin
      rd_ram_addx <= rd_ram_addx;
    end
end


assign  ch_fifo_data[31:0] = rd_ram1_dq_tmp[31:0];
assign  ch_fifo_mod [1:0]  = rd_ram1_dq_tmp[33:32];
assign  ch_fifo_eop        = rd_ram1_dq_tmp[34];
assign  ch_fifo_sop        = rd_ram1_dq_tmp[35];

assign  ch_fifo_par        = rd_ram2_dq_tmp[0];
assign  ch_fifo_err        = rd_ram2_dq_tmp[1];


//lose_pkt_cnt
always @(posedge sys_clk_100m)
begin
  if(~h_reset_n)
    begin
      lose_pkt_cnt<=16'd0;
    end
  else if(~s_reset_n)
    begin
      lose_pkt_cnt<=16'd0;
    end
  else if(wren_eop)
    begin
      if(rx_pkt_ram_full || rx_pkt_ram_full_tmp)      
        lose_pkt_cnt<=lose_pkt_cnt + 16'd1;
      else
        lose_pkt_cnt<=lose_pkt_cnt;      
    end    
  else
    begin
      lose_pkt_cnt<=lose_pkt_cnt;
    end
end
 


endmodule