link_phy_pl3_inst.v

VERILOG五POSPHY LEVEL3电路描述

// Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
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// net list, support information, device programming or simulation file, or
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	link_phy_pl3	link_phy_pl3_inst(
		.a_tfclk(a_tfclk_sig),
		.a_treset_n(a_treset_n_sig),
		.a_dtpa(a_dtpa_sig),
		.b_clk(b_clk_sig),
		.b_reset_n(b_reset_n_sig),
		.b1_ena(b1_ena_sig),
		.b1_dat(b1_dat_sig),
		.b1_sop(b1_sop_sig),
		.b1_eop(b1_eop_sig),
		.b1_err(b1_err_sig),
		.b1_mty(b1_mty_sig),
		.b2_ena(b2_ena_sig),
		.b2_dat(b2_dat_sig),
		.b2_sop(b2_sop_sig),
		.b2_eop(b2_eop_sig),
		.b2_err(b2_err_sig),
		.b2_mty(b2_mty_sig),
		.a_tenb(a_tenb_sig),
		.a_tsx(a_tsx_sig),
		.a_tdat(a_tdat_sig),
		.a_tsop(a_tsop_sig),
		.a_teop(a_teop_sig),
		.a_terr(a_terr_sig),
		.a_tmod(a_tmod_sig),
		.b1_dav(b1_dav_sig),
		.b2_dav(b2_dav_sig));