chip.vhd

Dallas 1-Wire ip 非常有用,不占用CPU的时间.

---------------------------------------------------------------
-- Project:			T121 digital audio generator
-- Package:			1-Wire Interface test chip
-- File:				chip.vhd
-- Version:			0.01
-- Date:				Jan. 17, 2001
-- Designer:		Henk Bliek
-- Customer:		int.
-- Description:	
-- Revision information:
-- 0.01	Henk Bliek - Jan. 17, 2001
--			* Initial version
---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity chip is
	port(	clk			:in std_logic;
			rst			:in std_logic;
			data			:inout std_logic_vector(7 downto 0);
			addr			:in std_logic_vector(1 downto 0);
			cs				:in std_logic;
			rd				:in std_logic;
			wr				:in std_logic;
			int			:out std_logic;
			wire			:inout std_logic);
end entity;

architecture rtl of chip is
	component onewire2 is
		port(	-- This clock must have a period of ~2us
				bitclk		:in std_logic;
				sysclk		:in std_logic;
				rst			:in std_logic;
				data_in		:in std_logic_vector(7 downto 0);
				data_out		:out std_logic_vector(7 downto 0);
				addr_in		:in std_logic_vector(1 downto 0);
				cs				:in std_logic;
				rd				:in std_logic;
				wr				:in std_logic;
				int			:out std_logic;
				-- The 1-Wire interface itself
				inwire		:in std_logic;
				outwire		:out std_logic);
	end component;

	signal data_out	:std_logic_vector(7 downto 0);
	signal wire_out	:std_logic;
begin
	U1: onewire2
		port map(	bitclk => clk,
						sysclk => clk,
						rst => rst,
						data_in => data,
						data_out => data_out,
						addr_in => addr,
						cs => cs,
						rd => rd,
						wr => wr,
						int => int,
						inwire => wire,
						outwire => wire_out);
						
	wire <= 'Z' when(wire_out = '1') else '0';
	data <= data_out when(rd = '0') else (others => 'Z');
end rtl;