test02.fnsim.qmsg

用quartusII编写的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 28 19:20:39 2007 " "Info: Processing started: Tue Aug 28 19:20:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test02 -c test02 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test02 -c test02 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test02.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file test02.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 test02-rtl " "Info: Found design unit 1: test02-rtl" {  } { { "test02.vhd" "" { Text "H:/FPGA/test02/test02.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 test02 " "Info: Found entity 1: test02" {  } { { "test02.vhd" "" { Text "H:/FPGA/test02/test02.vhd" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test02 " "Info: Elaborating entity \"test02\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "mincount test02.vhd(47) " "Warning (10540): VHDL Signal Declaration warning at test02.vhd(47): used explicit default value for signal \"mincount\" because signal was never assigned a value" {  } { { "test02.vhd" "" { Text "H:/FPGA/test02/test02.vhd" 47 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "PB_PulseOut test02.vhd(106) " "Warning (10492): VHDL Process Statement warning at test02.vhd(106): signal \"PB_PulseOut\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "test02.vhd" "" { Text "H:/FPGA/test02/test02.vhd" 106 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/aa/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/aa/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/aa/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/aa/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/aa/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/aa/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/aa/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/aa/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 19:20:41 2007 " "Info: Processing ended: Tue Aug 28 19:20:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}