test02.tan.rpt

用quartusII编写的

; N/A           ; None        ; -6.085 ns ; PDSwitch  ; Led[2]          ; clk      ;
; N/A           ; None        ; -6.086 ns ; PDSwitch  ; Led[3]          ; clk      ;
+---------------+-------------+-----------+-----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Aug 28 21:12:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test02 -c test02 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 132.26 MHz between source register "count[8]" and destination register "Led[3]" (period= 7.561 ns)
    Info: + Longest register to register delay is 7.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y5_N9; Fanout = 4; REG Node = 'count[8]'
        Info: 2: + IC(1.590 ns) + CELL(0.292 ns) = 1.882 ns; Loc. = LC_X11_Y4_N3; Fanout = 1; COMB Node = 'Equal~185'
        Info: 3: + IC(0.405 ns) + CELL(0.442 ns) = 2.729 ns; Loc. = LC_X11_Y4_N2; Fanout = 2; COMB Node = 'Equal~188'
        Info: 4: + IC(0.454 ns) + CELL(0.590 ns) = 3.773 ns; Loc. = LC_X11_Y4_N6; Fanout = 5; COMB Node = 'PB_valid~21'
        Info: 5: + IC(1.096 ns) + CELL(0.442 ns) = 5.311 ns; Loc. = LC_X11_Y4_N0; Fanout = 4; COMB Node = 'Led[0]~223'
        Info: 6: + IC(1.122 ns) + CELL(0.867 ns) = 7.300 ns; Loc. = LC_X10_Y4_N3; Fanout = 2; REG Node = 'Led[3]'
        Info: Total cell delay = 2.633 ns ( 36.07 % )
        Info: Total interconnect delay = 4.667 ns ( 63.93 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y4_N3; Fanout = 2; REG Node = 'Led[3]'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
        Info: - Longest clock path from clock "clk" to source register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X12_Y5_N9; Fanout = 4; REG Node = 'count[8]'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "Led[3]" (data pin = "PDSwitch", clock pin = "clk") is 6.839 ns
    Info: + Longest pin to register delay is 9.705 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_222; Fanout = 7; PIN Node = 'PDSwitch'
        Info: 2: + IC(6.788 ns) + CELL(0.575 ns) = 8.838 ns; Loc. = LC_X10_Y4_N1; Fanout = 2; COMB Node = 'Led[1]~212COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 8.918 ns; Loc. = LC_X10_Y4_N2; Fanout = 1; COMB Node = 'Led[2]~216COUT1_226'
        Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 9.705 ns; Loc. = LC_X10_Y4_N3; Fanout = 2; REG Node = 'Led[3]'
        Info: Total cell delay = 2.917 ns ( 30.06 % )
        Info: Total interconnect delay = 6.788 ns ( 69.94 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y4_N3; Fanout = 2; REG Node = 'Led[3]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "clk" to destination pin "Led_inv[0]" through register "Led[0]" is 7.785 ns
    Info: + Longest clock path from clock "clk" to source register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y4_N0; Fanout = 4; REG Node = 'Led[0]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.658 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N0; Fanout = 4; REG Node = 'Led[0]'
        Info: 2: + IC(2.534 ns) + CELL(2.124 ns) = 4.658 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'Led_inv[0]'
        Info: Total cell delay = 2.124 ns ( 45.60 % )
        Info: Total interconnect delay = 2.534 ns ( 54.40 % )
Info: th for register "DipSwitch_flop1" (data pin = "DipSwitch", clock pin = "clk") is -4.284 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y2_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.202 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'DipSwitch'
        Info: 2: + IC(5.618 ns) + CELL(0.115 ns) = 7.202 ns; Loc. = LC_X10_Y2_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 1.584 ns ( 21.99 % )
        Info: Total interconnect delay = 5.618 ns ( 78.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 28 21:12:13 2007
    Info: Elapsed time: 00:00:01