box.fit.eqn

用vhdl语言编写的基于fpga的波形发生器

--operation mode is normal

state.display_on_lut_out = state.hold & (next_command.display_on);
state.display_on = DFFEAS(state.display_on_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--state.display_off is state.display_off at LC_X14_Y11_N6
--operation mode is normal

state.display_off_lut_out = state.hold & (next_command.display_off);
state.display_off = DFFEAS(state.display_off_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L183 is state.display_clear~79 at LC_X14_Y12_N6
--operation mode is normal

A1L183 = A1L182 & !state.display_on & !state.display_off;


--state.display_set is state.display_set at LC_X15_Y13_N6
--operation mode is normal

state.display_set_lut_out = next_command.display_set & state.hold;
state.display_set = DFFEAS(state.display_set_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--state.hold is state.hold at LC_X15_Y13_N7
--operation mode is normal

state.hold_lut_out = state.toggle_e & (!state.hold);
state.hold = DFFEAS(state.hold_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L184 is state.display_clear~80 at LC_X15_Y13_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

state.toggle_e_qfbk = state.toggle_e;
A1L184 = !state.hold & (!state.toggle_e_qfbk & !state.display_set);

--state.toggle_e is state.toggle_e at LC_X15_Y13_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

state.toggle_e = DFFEAS(A1L184, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , A1L164, , , VCC);


--state.display_clear is state.display_clear at LC_X14_Y11_N5
--operation mode is normal

state.display_clear_lut_out = state.hold & next_command.display_clear;
state.display_clear = DFFEAS(state.display_clear_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--state.mode_set is state.mode_set at LC_X15_Y12_N3
--operation mode is normal

state.mode_set_lut_out = next_command.mode_set & state.hold;
state.mode_set = DFFEAS(state.mode_set_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--state.return_home is state.return_home at LC_X15_Y12_N1
--operation mode is normal

state.return_home_lut_out = next_command.return_home & (state.hold);
state.return_home = DFFEAS(state.return_home_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L185 is state.display_clear~81 at LC_X15_Y12_N8
--operation mode is normal

A1L185 = !state.display_clear & !state.mode_set & A1L184 & !state.return_home;


--CLK_400HZ is CLK_400HZ at LC_X16_Y10_N8
--operation mode is normal

CLK_400HZ_lut_out = !RES & (A1L112 $ !CLK_400HZ);
CLK_400HZ = DFFEAS(CLK_400HZ_lut_out, GLOBAL(CLK), VCC, , , , , , );


--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X22_Y7_N9
--operation mode is normal

C1_hub_tdo = AMPP_FUNCTION(!A1L5, C1L17, C1L14, C1L21, C1L20, !HB1_state[8]);


--HB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X25_Y8_N5
--operation mode is normal

HB1_state[4] = AMPP_FUNCTION(A1L5, HB1_state[3], HB1_state[7], HB1_state[4], VCC, A1L7);


--HB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X25_Y8_N0
--operation mode is normal

HB1_state[3] = AMPP_FUNCTION(A1L5, A1L7, HB1_state[2], VCC);


--FB7_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] at LC_X21_Y8_N8
--operation mode is normal

FB7_Q[2] = AMPP_FUNCTION(A1L5, FB3_Q[2], C1_CLRN_SIGNAL, C1L9);


--FB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X22_Y8_N1
--operation mode is normal

FB3_Q[2] = AMPP_FUNCTION(A1L5, J1L4, MB1_ir_loaded_address_reg[1], FB3_Q[3], C1L22, C1_CLRN_SIGNAL, HB1_state[4], FB3L4);


--C1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL at LC_X27_Y7_N2
--operation mode is normal

C1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, HB1_state[1], FB1_Q[0], VCC);


--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X22_Y8_N5
--operation mode is normal

C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, HB1_state[4], HB1_state[8], VCC);


--C1L33 is sld_hub:sld_hub_inst|node_ena~42 at LC_X21_Y8_N5
--operation mode is normal

C1L33 = AMPP_FUNCTION(FB8_Q[0], FB2_Q[0]);


--FB9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X24_Y7_N3
--operation mode is normal

FB9_Q[0] = AMPP_FUNCTION(A1L5, FB3_Q[8], altera_internal_jtag, VCC, C1L23);


--JB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2] at LC_X26_Y7_N4
--operation mode is normal

JB1_dffe1a[2] = AMPP_FUNCTION(A1L5, FB3_Q[1], FB3_Q[2], FB3_Q[3], C1L31, C1_CLRN_SIGNAL, C1L5);


--C1L24 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~124 at LC_X24_Y7_N5
--operation mode is normal

C1L24 = AMPP_FUNCTION(FB9_Q[0], FB2_Q[0], JB1_dffe1a[2]);


--C1L25 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125 at LC_X20_Y7_N1
--operation mode is normal

C1L25 = AMPP_FUNCTION(C1L24, C1_OK_TO_UPDATE_IR_Q, C1L33, HB1_state[5]);


--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 at LC_X26_Y7_N9
--operation mode is normal

C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, C1L6, C1L7, M5_dffs[0], M5_dffs[1], HB1_state[0], HB1_state[12]);


--C1L31 is sld_hub:sld_hub_inst|jtag_debug_mode~2 at LC_X26_Y7_N3
--operation mode is normal

C1L31 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);


--HB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X27_Y6_N0
--operation mode is normal

HB1_state[12] = AMPP_FUNCTION(A1L5, HB1_state[11], HB1_state[10], VCC, !A1L7);


--HB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X27_Y6_N6
--operation mode is normal

HB1_state[2] = AMPP_FUNCTION(A1L5, HB1_state[1], HB1_state[8], HB1_state[15], VCC, !A1L7);


--C1L32 is sld_hub:sld_hub_inst|jtag_debug_mode~171 at LC_X26_Y7_N6
--operation mode is normal

C1L32 = AMPP_FUNCTION(A1L7, HB1_state[12], HB1_state[2]);


--HB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] at LC_X27_Y6_N5
--operation mode is normal

HB1_state[15] = AMPP_FUNCTION(A1L5, HB1_state[14], HB1_state[12], VCC, !A1L7);


--HB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X27_Y6_N2
--operation mode is normal

HB1_state[0] = AMPP_FUNCTION(A1L5, A1L7, HB1_state[0], HB1L19, HB1_state[9], VCC);


--FB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] at LC_X22_Y6_N4
--operation mode is normal

FB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, C1_CLRN_SIGNAL, HB1_state[4], C1L27);


--C1L23 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 at LC_X24_Y7_N8
--operation mode is normal

C1L23 = AMPP_FUNCTION(HB1_state[4], C1_OK_TO_UPDATE_IR_Q, C1_jtag_debug_mode_usr1, A1L7);


--M5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X26_Y6_N9
--operation mode is normal

M5_dffs[1] = AMPP_FUNCTION(A1L5, M5_dffs[2], HB1_state[0], HB1_state[11]);


--M5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X26_Y6_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[8] = AMPP_FUNCTION(A1L5, M5_dffs[9], HB1_state[0], GND, HB1_state[11]);


--M5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X26_Y6_N7
--operation mode is normal

M5_dffs[7] = AMPP_FUNCTION(A1L5, M5_dffs[8], HB1_state[0], HB1_state[11]);


--M5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X26_Y6_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[6] = AMPP_FUNCTION(A1L5, M5_dffs[7], HB1_state[0], GND, HB1_state[11]);


--C1L6 is sld_hub:sld_hub_inst|Equal~182 at LC_X26_Y6_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L6 = AMPP_FUNCTION(M5_dffs[7], M5_dffs[6], M5_dffs[8]);