box.fit.eqn

用vhdl语言编写的基于fpga的波形发生器

LB1_q_b[0]_PORT_A_address_reg = DFFE(LB1_q_b[0]_PORT_A_address, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[0]_PORT_B_address_reg = DFFE(LB1_q_b[0]_PORT_B_address, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_write_enable = GND;
LB1_q_b[0]_PORT_A_write_enable_reg = DFFE(LB1_q_b[0]_PORT_A_write_enable, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_write_enable = MB1L2;
LB1_q_b[0]_PORT_B_write_enable_reg = DFFE(LB1_q_b[0]_PORT_B_write_enable, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_clock_0 = GLOBAL(NB1__clk0);
LB1_q_b[0]_clock_1 = GLOBAL(A1L5);
LB1_q_b[0]_PORT_B_data_out = MEMORY(LB1_q_b[0]_PORT_A_data_in_reg, LB1_q_b[0]_PORT_B_data_in_reg, LB1_q_b[0]_PORT_A_address_reg, LB1_q_b[0]_PORT_B_address_reg, LB1_q_b[0]_PORT_A_write_enable_reg, LB1_q_b[0]_PORT_B_write_enable_reg, , , LB1_q_b[0]_clock_0, LB1_q_b[0]_clock_1, , , , );
LB1_q_b[4] = LB1_q_b[0]_PORT_B_data_out[4];

--LB1_q_b[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[3] at M4K_X17_Y8
LB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
LB1_q_b[0]_PORT_A_data_in_reg = DFFE(LB1_q_b[0]_PORT_A_data_in, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_data_in = BUS(MB1_ram_rom_data_reg[0], MB1_ram_rom_data_reg[1], MB1_ram_rom_data_reg[2], MB1_ram_rom_data_reg[3], MB1_ram_rom_data_reg[4], MB1_ram_rom_data_reg[5], MB1_ram_rom_data_reg[6], MB1_ram_rom_data_reg[7]);
LB1_q_b[0]_PORT_B_data_in_reg = DFFE(LB1_q_b[0]_PORT_B_data_in, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[0]_PORT_A_address_reg = DFFE(LB1_q_b[0]_PORT_A_address, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[0]_PORT_B_address_reg = DFFE(LB1_q_b[0]_PORT_B_address, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_write_enable = GND;
LB1_q_b[0]_PORT_A_write_enable_reg = DFFE(LB1_q_b[0]_PORT_A_write_enable, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_write_enable = MB1L2;
LB1_q_b[0]_PORT_B_write_enable_reg = DFFE(LB1_q_b[0]_PORT_B_write_enable, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_clock_0 = GLOBAL(NB1__clk0);
LB1_q_b[0]_clock_1 = GLOBAL(A1L5);
LB1_q_b[0]_PORT_B_data_out = MEMORY(LB1_q_b[0]_PORT_A_data_in_reg, LB1_q_b[0]_PORT_B_data_in_reg, LB1_q_b[0]_PORT_A_address_reg, LB1_q_b[0]_PORT_B_address_reg, LB1_q_b[0]_PORT_A_write_enable_reg, LB1_q_b[0]_PORT_B_write_enable_reg, , , LB1_q_b[0]_clock_0, LB1_q_b[0]_clock_1, , , , );
LB1_q_b[3] = LB1_q_b[0]_PORT_B_data_out[3];

--LB1_q_b[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[2] at M4K_X17_Y8
LB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
LB1_q_b[0]_PORT_A_data_in_reg = DFFE(LB1_q_b[0]_PORT_A_data_in, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_data_in = BUS(MB1_ram_rom_data_reg[0], MB1_ram_rom_data_reg[1], MB1_ram_rom_data_reg[2], MB1_ram_rom_data_reg[3], MB1_ram_rom_data_reg[4], MB1_ram_rom_data_reg[5], MB1_ram_rom_data_reg[6], MB1_ram_rom_data_reg[7]);
LB1_q_b[0]_PORT_B_data_in_reg = DFFE(LB1_q_b[0]_PORT_B_data_in, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[0]_PORT_A_address_reg = DFFE(LB1_q_b[0]_PORT_A_address, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[0]_PORT_B_address_reg = DFFE(LB1_q_b[0]_PORT_B_address, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_write_enable = GND;
LB1_q_b[0]_PORT_A_write_enable_reg = DFFE(LB1_q_b[0]_PORT_A_write_enable, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_write_enable = MB1L2;
LB1_q_b[0]_PORT_B_write_enable_reg = DFFE(LB1_q_b[0]_PORT_B_write_enable, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_clock_0 = GLOBAL(NB1__clk0);
LB1_q_b[0]_clock_1 = GLOBAL(A1L5);
LB1_q_b[0]_PORT_B_data_out = MEMORY(LB1_q_b[0]_PORT_A_data_in_reg, LB1_q_b[0]_PORT_B_data_in_reg, LB1_q_b[0]_PORT_A_address_reg, LB1_q_b[0]_PORT_B_address_reg, LB1_q_b[0]_PORT_A_write_enable_reg, LB1_q_b[0]_PORT_B_write_enable_reg, , , LB1_q_b[0]_clock_0, LB1_q_b[0]_clock_1, , , , );
LB1_q_b[2] = LB1_q_b[0]_PORT_B_data_out[2];

--LB1_q_b[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[1] at M4K_X17_Y8
LB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
LB1_q_b[0]_PORT_A_data_in_reg = DFFE(LB1_q_b[0]_PORT_A_data_in, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_data_in = BUS(MB1_ram_rom_data_reg[0], MB1_ram_rom_data_reg[1], MB1_ram_rom_data_reg[2], MB1_ram_rom_data_reg[3], MB1_ram_rom_data_reg[4], MB1_ram_rom_data_reg[5], MB1_ram_rom_data_reg[6], MB1_ram_rom_data_reg[7]);
LB1_q_b[0]_PORT_B_data_in_reg = DFFE(LB1_q_b[0]_PORT_B_data_in, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[0]_PORT_A_address_reg = DFFE(LB1_q_b[0]_PORT_A_address, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[0]_PORT_B_address_reg = DFFE(LB1_q_b[0]_PORT_B_address, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_write_enable = GND;
LB1_q_b[0]_PORT_A_write_enable_reg = DFFE(LB1_q_b[0]_PORT_A_write_enable, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_write_enable = MB1L2;
LB1_q_b[0]_PORT_B_write_enable_reg = DFFE(LB1_q_b[0]_PORT_B_write_enable, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_clock_0 = GLOBAL(NB1__clk0);
LB1_q_b[0]_clock_1 = GLOBAL(A1L5);
LB1_q_b[0]_PORT_B_data_out = MEMORY(LB1_q_b[0]_PORT_A_data_in_reg, LB1_q_b[0]_PORT_B_data_in_reg, LB1_q_b[0]_PORT_A_address_reg, LB1_q_b[0]_PORT_B_address_reg, LB1_q_b[0]_PORT_A_write_enable_reg, LB1_q_b[0]_PORT_B_write_enable_reg, , , LB1_q_b[0]_clock_0, LB1_q_b[0]_clock_1, , , , );
LB1_q_b[1] = LB1_q_b[0]_PORT_B_data_out[1];


--A1L106Q is LCD_RS~reg0 at LC_X15_Y12_N6
--operation mode is normal

A1L106Q_lut_out = A1L183 & (A1L185 # !A1L184 & A1L106Q) # !A1L183 & !A1L184 & (A1L106Q);
A1L106Q = DFFEAS(A1L106Q_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L104Q is LCD_E~reg0 at LC_X14_Y13_N3
--operation mode is normal

A1L104Q_lut_out = state.display_set & (A1L104Q) # !state.display_set & (state.hold & (A1L104Q) # !state.hold & state.toggle_e);
A1L104Q = DFFEAS(A1L104Q_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y10_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y10_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y10_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y10_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);


--HB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X20_Y7_N3
--operation mode is normal

HB1_state[5] = AMPP_FUNCTION(A1L5, A1L7, HB1_state[3], HB1_state[4], VCC);


--FB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X21_Y7_N3
--operation mode is normal

FB5_Q[2] = AMPP_FUNCTION(A1L5, FB3_Q[2], FB7_Q[2], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X27_Y7_N4
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, C1_jtag_debug_mode, HB1_state[15], C1L31, C1L32, HB1_state[0]);


--FB8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X19_Y8_N9
--operation mode is normal

FB8_Q[0] = AMPP_FUNCTION(A1L5, FB3_Q[8], altera_internal_jtag, C1_CLRN_SIGNAL, C1L23);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X26_Y7_N2
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, C1L6, C1L7, M5_dffs[0], M5_dffs[1], HB1_state[0], HB1_state[12]);


--FB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X23_Y9_N0
--operation mode is normal

FB2_Q[0] = AMPP_FUNCTION(A1L5, FB9_Q[0], C1L1, JB1_dffe1a[1], FB2_Q[0], C1_CLRN_SIGNAL);


--MB1L64 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~21 at LC_X19_Y8_N0
--operation mode is normal

MB1L64 = AMPP_FUNCTION(C1_jtag_debug_mode, FB8_Q[0], FB2_Q[0], C1_jtag_debug_mode_usr1);


--MB1L2 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X20_Y7_N4
--operation mode is normal

MB1L2 = AMPP_FUNCTION(FB5_Q[2], MB1L64, HB1_state[5]);


--NB1__clk0 is PLLU:u2|altpll:altpll_component|_clk0 at PLL_1
NB1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GLOBAL(RES)), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--Q1[0] is Q1[0] at LC_X16_Y7_N0
--operation mode is arithmetic

Q1[0]_lut_out = !Q1[0];
Q1[0] = DFFEAS(Q1[0]_lut_out, GLOBAL(NB1__clk0), VCC, , , ~GND, , , A1L142);

--A1L140 is Q1[0]~473 at LC_X16_Y7_N0
--operation mode is arithmetic

A1L140_cout_0 = Q1[0];
A1L140 = CARRY(A1L140_cout_0);

--A1L141 is Q1[0]~473COUT1_506 at LC_X16_Y7_N0
--operation mode is arithmetic

A1L141_cout_1 = Q1[0];
A1L141 = CARRY(A1L141_cout_1);


--Q1[1] is Q1[1] at LC_X16_Y7_N1
--operation mode is arithmetic

Q1[1]_lut_out = Q1[1] $ (A1L140);
Q1[1] = DFFEAS(Q1[1]_lut_out, GLOBAL(NB1__clk0), VCC, , , ~GND, , , A1L142);

--A1L144 is Q1[1]~477 at LC_X16_Y7_N1
--operation mode is arithmetic

A1L144_cout_0 = !A1L140 # !Q1[1];
A1L144 = CARRY(A1L144_cout_0);

--A1L145 is Q1[1]~477COUT1_507 at LC_X16_Y7_N1
--operation mode is arithmetic

A1L145_cout_1 = !A1L141 # !Q1[1];
A1L145 = CARRY(A1L145_cout_1);


--Q1[2] is Q1[2] at LC_X16_Y7_N2
--operation mode is arithmetic

Q1[2]_lut_out = Q1[2] $ (!A1L144);
Q1[2] = DFFEAS(Q1[2]_lut_out, GLOBAL(NB1__clk0), VCC, , , ~GND, , , A1L142);

--A1L147 is Q1[2]~481 at LC_X16_Y7_N2
--operation mode is arithmetic

A1L147_cout_0 = Q1[2] & (!A1L144);
A1L147 = CARRY(A1L147_cout_0);

--A1L148 is Q1[2]~481COUT1_508 at LC_X16_Y7_N2
--operation mode is arithmetic

A1L148_cout_1 = Q1[2] & (!A1L145);
A1L148 = CARRY(A1L148_cout_1);


--Q1[3] is Q1[3] at LC_X16_Y7_N3
--operation mode is arithmetic

Q1[3]_lut_out = Q1[3] $ A1L147;
Q1[3] = DFFEAS(Q1[3]_lut_out, GLOBAL(NB1__clk0), VCC, , , ~GND, , , A1L142);

--A1L150 is Q1[3]~485 at LC_X16_Y7_N3
--operation mode is arithmetic

A1L150_cout_0 = !A1L147 # !Q1[3];
A1L150 = CARRY(A1L150_cout_0);

--A1L151 is Q1[3]~485COUT1 at LC_X16_Y7_N3
--operation mode is arithmetic

A1L151_cout_1 = !A1L148 # !Q1[3];
A1L151 = CARRY(A1L151_cout_1);


--Q1[4] is Q1[4] at LC_X16_Y7_N4
--operation mode is arithmetic

Q1[4]_lut_out = Q1[4] $ !A1L150;
Q1[4] = DFFEAS(Q1[4]_lut_out, GLOBAL(NB1__clk0), VCC, , , ~GND, , , A1L142);

--A1L153 is Q1[4]~489 at LC_X16_Y7_N4
--operation mode is arithmetic

A1L153 = A1L154;


--Q1[5] is Q1[5] at LC_X16_Y7_N5
--operation mode is arithmetic

Q1[5]_carry_eqn = (!A1L153 & GND) # (A1L153 & VCC);
Q1[5]_lut_out = Q1[5] $ Q1[5]_carry_eqn;