cntr_tia.tdf

用vhdl语言编写的基于fpga的波形发生器

--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" lpm_modulus=16 lpm_width=4 aclr clock q
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 4 
SUBDESIGN cntr_tia
( 
	aclr	:	input;
	clock	:	input;
	q[3..0]	:	output;
) 
VARIABLE 
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "11AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	aclr_actual	: WIRE;
	clk_en	: NODE;
	data[3..0]	: NODE;
	safe_q[3..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;

BEGIN 
	counter_cella[3..0].aclr = aclr_actual;
	counter_cella[3..0].aload = B"0000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[3..0].clk = clock;
	counter_cella[3..0].dataa = safe_q[];
	counter_cella[3..0].datab = B"0000";
	counter_cella[3..0].datac = data[];
	counter_cella[3].datad = B"1";
	counter_cella[3..0].ena = clk_en;
	counter_cella[3..0].sclr = sclr;
	counter_cella[3..0].sload = sload;
	aclr_actual = aclr;
	clk_en = VCC;
	data[] = GND;
	q[] = safe_q[];
	safe_q[] = counter_cella[3..0].regout;
	sclr = GND;
	sload = GND;
END;
--VALID FILE