📄 box.tan.rpt
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; PLLU:u2|altpll:altpll_component|_clk0 ; ; PLL output ; 100.01 MHz ; 0.000 ns ; 0.000 ns ; CLK ; 25 ; 12 ; -1.885 ns ; ;
; CLK ; ; User Pin ; 48.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; auto_stp_external_clock_0 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLLU:u2|altpll:altpll_component|_clk0' ;
+----------+-----------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+----------+-----------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+-----------------------------+---------------------------+-------------------------+
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg1 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg1 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg2 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg2 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg3 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg3 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg4 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg4 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg5 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg5 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg6 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg6 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 4.923 ns ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg7 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg7 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.242 ns ; 4.319 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[0] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[1] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[2] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[3] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[4] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[5] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[6] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 6.908 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; Q1[7] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.830 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[0] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[1] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[2] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[3] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[4] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[5] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[6] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.188 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; Q1[7] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.550 ns ;
; 7.220 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[6] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg6 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.480 ns ;
; 7.229 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[3] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg3 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.471 ns ;
; 7.254 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[2] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg2 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.446 ns ;
; 7.371 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[1] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg1 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.329 ns ;
; 7.390 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[4] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg4 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.310 ns ;
; 7.400 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[0] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg0 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.300 ns ;
; 7.403 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[7] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg7 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.297 ns ;
; 7.443 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[5] ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_address_reg5 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.700 ns ; 2.257 ns ;
; 7.467 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[1] ; Q1[5] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.271 ns ;
; 7.467 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[1] ; Q1[6] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.271 ns ;
; 7.467 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; Q1[1] ; Q1[7] ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 9.999 ns ; 9.738 ns ; 2.271 ns ;
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