box.tan.rpt

用vhdl语言编写的基于fpga的波形发生器

+------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Type                                                 ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                 ; To                                                                                                                                  ; From Clock                            ; To Clock                              ; Failed Paths ;
+------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Worst-case tsu                                       ; N/A       ; None                             ; 9.992 ns                         ; DS0                                                                                                                                                                  ; Q1[7]                                                                                                                               ; --                                    ; CLK                                   ; 0            ;
; Worst-case tco                                       ; N/A       ; None                             ; 15.173 ns                        ; DATA_BUS_VALUE[7]                                                                                                                                                    ; DATA_BUS[7]                                                                                                                         ; CLK                                   ; --                                    ; 0            ;
; Worst-case tpd                                       ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                             ; altera_reserved_tdo                                                                                                                 ; --                                    ; --                                    ; 0            ;
; Worst-case th                                        ; N/A       ; None                             ; 2.503 ns                         ; altera_internal_jtag                                                                                                                                                 ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]              ; --                                    ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Clock Setup: 'PLLU:u2|altpll:altpll_component|_clk0' ; 4.923 ns  ; 100.01 MHz ( period = 9.999 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0                                  ; allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLK'                                   ; 13.463 ns ; 48.00 MHz ( period = 20.833 ns ) ; 135.69 MHz ( period = 7.370 ns ) ; CLK_COUNT_400HZ[8]                                                                                                                                                   ; CLK_COUNT_400HZ[5]                                                                                                                  ; CLK                                   ; CLK                                   ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'          ; N/A       ; None                             ; 95.13 MHz ( period = 10.512 ns ) ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]                                                                                              ; sld_hub:sld_hub_inst|hub_tdo                                                                                                        ; altera_internal_jtag~TCKUTAP          ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Clock Setup: 'auto_stp_external_clock_0'             ; N/A       ; None                             ; 130.36 MHz ( period = 7.671 ns ) ; sld_signaltap:BOX|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|safe_q[1] ; sld_signaltap:BOX|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_tjb2:auto_generated|ram_block1a0~porta_datain_reg0     ; auto_stp_external_clock_0             ; auto_stp_external_clock_0             ; 0            ;
; Clock Hold: 'CLK'                                    ; 1.040 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; next_command.reset3                                                                                                                                                  ; next_command.reset3                                                                                                                 ; CLK                                   ; CLK                                   ; 0            ;
; Clock Hold: 'PLLU:u2|altpll:altpll_component|_clk0'  ; 1.326 ns  ; 100.01 MHz ( period = 9.999 ns ) ; N/A                              ; Q1[0]                                                                                                                                                                ; Q1[0]                                                                                                                               ; PLLU:u2|altpll:altpll_component|_clk0 ; PLLU:u2|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                         ;           ;                                  ;                                  ;                                                                                                                                                                      ;                                                                                                                                     ;                                       ;                                       ; 0            ;
+------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                        ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                       ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+