box.map.eqn

用vhdl语言编写的基于fpga的波形发生器

-- Copyright (C) 1991-2006 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--LB1_q_a[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[0]_PORT_A_data_in = VCC;
LB1_q_a[0]_PORT_A_data_in_reg = DFFE(LB1_q_a[0]_PORT_A_data_in, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0]_PORT_B_data_in = MB1_ram_rom_data_reg[0];
LB1_q_a[0]_PORT_B_data_in_reg = DFFE(LB1_q_a[0]_PORT_B_data_in, LB1_q_a[0]_clock_1, , , );
LB1_q_a[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[0]_PORT_A_address_reg = DFFE(LB1_q_a[0]_PORT_A_address, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[0]_PORT_B_address_reg = DFFE(LB1_q_a[0]_PORT_B_address, LB1_q_a[0]_clock_1, , , );
LB1_q_a[0]_PORT_A_write_enable = GND;
LB1_q_a[0]_PORT_A_write_enable_reg = DFFE(LB1_q_a[0]_PORT_A_write_enable, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0]_PORT_B_write_enable = MB1L2;
LB1_q_a[0]_PORT_B_write_enable_reg = DFFE(LB1_q_a[0]_PORT_B_write_enable, LB1_q_a[0]_clock_1, , , );
LB1_q_a[0]_clock_0 = NB1__clk0;
LB1_q_a[0]_clock_1 = A1L5;
LB1_q_a[0]_PORT_A_data_out = MEMORY(LB1_q_a[0]_PORT_A_data_in_reg, LB1_q_a[0]_PORT_B_data_in_reg, LB1_q_a[0]_PORT_A_address_reg, LB1_q_a[0]_PORT_B_address_reg, LB1_q_a[0]_PORT_A_write_enable_reg, LB1_q_a[0]_PORT_B_write_enable_reg, , , LB1_q_a[0]_clock_0, LB1_q_a[0]_clock_1, , , , );
LB1_q_a[0] = LB1_q_a[0]_PORT_A_data_out[0];

--LB1_q_b[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[0]
LB1_q_b[0]_PORT_A_data_in = VCC;
LB1_q_b[0]_PORT_A_data_in_reg = DFFE(LB1_q_b[0]_PORT_A_data_in, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_data_in = MB1_ram_rom_data_reg[0];
LB1_q_b[0]_PORT_B_data_in_reg = DFFE(LB1_q_b[0]_PORT_B_data_in, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[0]_PORT_A_address_reg = DFFE(LB1_q_b[0]_PORT_A_address, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[0]_PORT_B_address_reg = DFFE(LB1_q_b[0]_PORT_B_address, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_PORT_A_write_enable = GND;
LB1_q_b[0]_PORT_A_write_enable_reg = DFFE(LB1_q_b[0]_PORT_A_write_enable, LB1_q_b[0]_clock_0, , , );
LB1_q_b[0]_PORT_B_write_enable = MB1L2;
LB1_q_b[0]_PORT_B_write_enable_reg = DFFE(LB1_q_b[0]_PORT_B_write_enable, LB1_q_b[0]_clock_1, , , );
LB1_q_b[0]_clock_0 = NB1__clk0;
LB1_q_b[0]_clock_1 = A1L5;
LB1_q_b[0]_PORT_B_data_out = MEMORY(LB1_q_b[0]_PORT_A_data_in_reg, LB1_q_b[0]_PORT_B_data_in_reg, LB1_q_b[0]_PORT_A_address_reg, LB1_q_b[0]_PORT_B_address_reg, LB1_q_b[0]_PORT_A_write_enable_reg, LB1_q_b[0]_PORT_B_write_enable_reg, , , LB1_q_b[0]_clock_0, LB1_q_b[0]_clock_1, , , , );
LB1_q_b[0] = LB1_q_b[0]_PORT_B_data_out[0];


--LB1_q_a[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[1]_PORT_A_data_in = VCC;
LB1_q_a[1]_PORT_A_data_in_reg = DFFE(LB1_q_a[1]_PORT_A_data_in, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1]_PORT_B_data_in = MB1_ram_rom_data_reg[1];
LB1_q_a[1]_PORT_B_data_in_reg = DFFE(LB1_q_a[1]_PORT_B_data_in, LB1_q_a[1]_clock_1, , , );
LB1_q_a[1]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[1]_PORT_A_address_reg = DFFE(LB1_q_a[1]_PORT_A_address, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[1]_PORT_B_address_reg = DFFE(LB1_q_a[1]_PORT_B_address, LB1_q_a[1]_clock_1, , , );
LB1_q_a[1]_PORT_A_write_enable = GND;
LB1_q_a[1]_PORT_A_write_enable_reg = DFFE(LB1_q_a[1]_PORT_A_write_enable, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1]_PORT_B_write_enable = MB1L2;
LB1_q_a[1]_PORT_B_write_enable_reg = DFFE(LB1_q_a[1]_PORT_B_write_enable, LB1_q_a[1]_clock_1, , , );
LB1_q_a[1]_clock_0 = NB1__clk0;
LB1_q_a[1]_clock_1 = A1L5;
LB1_q_a[1]_PORT_A_data_out = MEMORY(LB1_q_a[1]_PORT_A_data_in_reg, LB1_q_a[1]_PORT_B_data_in_reg, LB1_q_a[1]_PORT_A_address_reg, LB1_q_a[1]_PORT_B_address_reg, LB1_q_a[1]_PORT_A_write_enable_reg, LB1_q_a[1]_PORT_B_write_enable_reg, , , LB1_q_a[1]_clock_0, LB1_q_a[1]_clock_1, , , , );
LB1_q_a[1] = LB1_q_a[1]_PORT_A_data_out[0];

--LB1_q_b[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[1]
LB1_q_b[1]_PORT_A_data_in = VCC;
LB1_q_b[1]_PORT_A_data_in_reg = DFFE(LB1_q_b[1]_PORT_A_data_in, LB1_q_b[1]_clock_0, , , );
LB1_q_b[1]_PORT_B_data_in = MB1_ram_rom_data_reg[1];
LB1_q_b[1]_PORT_B_data_in_reg = DFFE(LB1_q_b[1]_PORT_B_data_in, LB1_q_b[1]_clock_1, , , );
LB1_q_b[1]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[1]_PORT_A_address_reg = DFFE(LB1_q_b[1]_PORT_A_address, LB1_q_b[1]_clock_0, , , );
LB1_q_b[1]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[1]_PORT_B_address_reg = DFFE(LB1_q_b[1]_PORT_B_address, LB1_q_b[1]_clock_1, , , );
LB1_q_b[1]_PORT_A_write_enable = GND;
LB1_q_b[1]_PORT_A_write_enable_reg = DFFE(LB1_q_b[1]_PORT_A_write_enable, LB1_q_b[1]_clock_0, , , );
LB1_q_b[1]_PORT_B_write_enable = MB1L2;
LB1_q_b[1]_PORT_B_write_enable_reg = DFFE(LB1_q_b[1]_PORT_B_write_enable, LB1_q_b[1]_clock_1, , , );
LB1_q_b[1]_clock_0 = NB1__clk0;
LB1_q_b[1]_clock_1 = A1L5;
LB1_q_b[1]_PORT_B_data_out = MEMORY(LB1_q_b[1]_PORT_A_data_in_reg, LB1_q_b[1]_PORT_B_data_in_reg, LB1_q_b[1]_PORT_A_address_reg, LB1_q_b[1]_PORT_B_address_reg, LB1_q_b[1]_PORT_A_write_enable_reg, LB1_q_b[1]_PORT_B_write_enable_reg, , , LB1_q_b[1]_clock_0, LB1_q_b[1]_clock_1, , , , );
LB1_q_b[1] = LB1_q_b[1]_PORT_B_data_out[0];


--LB1_q_a[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[2]_PORT_A_data_in = VCC;
LB1_q_a[2]_PORT_A_data_in_reg = DFFE(LB1_q_a[2]_PORT_A_data_in, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2]_PORT_B_data_in = MB1_ram_rom_data_reg[2];
LB1_q_a[2]_PORT_B_data_in_reg = DFFE(LB1_q_a[2]_PORT_B_data_in, LB1_q_a[2]_clock_1, , , );
LB1_q_a[2]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[2]_PORT_A_address_reg = DFFE(LB1_q_a[2]_PORT_A_address, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[2]_PORT_B_address_reg = DFFE(LB1_q_a[2]_PORT_B_address, LB1_q_a[2]_clock_1, , , );
LB1_q_a[2]_PORT_A_write_enable = GND;
LB1_q_a[2]_PORT_A_write_enable_reg = DFFE(LB1_q_a[2]_PORT_A_write_enable, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2]_PORT_B_write_enable = MB1L2;
LB1_q_a[2]_PORT_B_write_enable_reg = DFFE(LB1_q_a[2]_PORT_B_write_enable, LB1_q_a[2]_clock_1, , , );
LB1_q_a[2]_clock_0 = NB1__clk0;
LB1_q_a[2]_clock_1 = A1L5;
LB1_q_a[2]_PORT_A_data_out = MEMORY(LB1_q_a[2]_PORT_A_data_in_reg, LB1_q_a[2]_PORT_B_data_in_reg, LB1_q_a[2]_PORT_A_address_reg, LB1_q_a[2]_PORT_B_address_reg, LB1_q_a[2]_PORT_A_write_enable_reg, LB1_q_a[2]_PORT_B_write_enable_reg, , , LB1_q_a[2]_clock_0, LB1_q_a[2]_clock_1, , , , );
LB1_q_a[2] = LB1_q_a[2]_PORT_A_data_out[0];

--LB1_q_b[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[2]
LB1_q_b[2]_PORT_A_data_in = VCC;
LB1_q_b[2]_PORT_A_data_in_reg = DFFE(LB1_q_b[2]_PORT_A_data_in, LB1_q_b[2]_clock_0, , , );
LB1_q_b[2]_PORT_B_data_in = MB1_ram_rom_data_reg[2];
LB1_q_b[2]_PORT_B_data_in_reg = DFFE(LB1_q_b[2]_PORT_B_data_in, LB1_q_b[2]_clock_1, , , );
LB1_q_b[2]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[2]_PORT_A_address_reg = DFFE(LB1_q_b[2]_PORT_A_address, LB1_q_b[2]_clock_0, , , );
LB1_q_b[2]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[2]_PORT_B_address_reg = DFFE(LB1_q_b[2]_PORT_B_address, LB1_q_b[2]_clock_1, , , );
LB1_q_b[2]_PORT_A_write_enable = GND;
LB1_q_b[2]_PORT_A_write_enable_reg = DFFE(LB1_q_b[2]_PORT_A_write_enable, LB1_q_b[2]_clock_0, , , );
LB1_q_b[2]_PORT_B_write_enable = MB1L2;
LB1_q_b[2]_PORT_B_write_enable_reg = DFFE(LB1_q_b[2]_PORT_B_write_enable, LB1_q_b[2]_clock_1, , , );
LB1_q_b[2]_clock_0 = NB1__clk0;
LB1_q_b[2]_clock_1 = A1L5;
LB1_q_b[2]_PORT_B_data_out = MEMORY(LB1_q_b[2]_PORT_A_data_in_reg, LB1_q_b[2]_PORT_B_data_in_reg, LB1_q_b[2]_PORT_A_address_reg, LB1_q_b[2]_PORT_B_address_reg, LB1_q_b[2]_PORT_A_write_enable_reg, LB1_q_b[2]_PORT_B_write_enable_reg, , , LB1_q_b[2]_clock_0, LB1_q_b[2]_clock_1, , , , );
LB1_q_b[2] = LB1_q_b[2]_PORT_B_data_out[0];


--LB1_q_a[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[3]_PORT_A_data_in = VCC;
LB1_q_a[3]_PORT_A_data_in_reg = DFFE(LB1_q_a[3]_PORT_A_data_in, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3]_PORT_B_data_in = MB1_ram_rom_data_reg[3];
LB1_q_a[3]_PORT_B_data_in_reg = DFFE(LB1_q_a[3]_PORT_B_data_in, LB1_q_a[3]_clock_1, , , );
LB1_q_a[3]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[3]_PORT_A_address_reg = DFFE(LB1_q_a[3]_PORT_A_address, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[3]_PORT_B_address_reg = DFFE(LB1_q_a[3]_PORT_B_address, LB1_q_a[3]_clock_1, , , );
LB1_q_a[3]_PORT_A_write_enable = GND;
LB1_q_a[3]_PORT_A_write_enable_reg = DFFE(LB1_q_a[3]_PORT_A_write_enable, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3]_PORT_B_write_enable = MB1L2;
LB1_q_a[3]_PORT_B_write_enable_reg = DFFE(LB1_q_a[3]_PORT_B_write_enable, LB1_q_a[3]_clock_1, , , );
LB1_q_a[3]_clock_0 = NB1__clk0;
LB1_q_a[3]_clock_1 = A1L5;
LB1_q_a[3]_PORT_A_data_out = MEMORY(LB1_q_a[3]_PORT_A_data_in_reg, LB1_q_a[3]_PORT_B_data_in_reg, LB1_q_a[3]_PORT_A_address_reg, LB1_q_a[3]_PORT_B_address_reg, LB1_q_a[3]_PORT_A_write_enable_reg, LB1_q_a[3]_PORT_B_write_enable_reg, , , LB1_q_a[3]_clock_0, LB1_q_a[3]_clock_1, , , , );
LB1_q_a[3] = LB1_q_a[3]_PORT_A_data_out[0];

--LB1_q_b[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[3]
LB1_q_b[3]_PORT_A_data_in = VCC;
LB1_q_b[3]_PORT_A_data_in_reg = DFFE(LB1_q_b[3]_PORT_A_data_in, LB1_q_b[3]_clock_0, , , );
LB1_q_b[3]_PORT_B_data_in = MB1_ram_rom_data_reg[3];
LB1_q_b[3]_PORT_B_data_in_reg = DFFE(LB1_q_b[3]_PORT_B_data_in, LB1_q_b[3]_clock_1, , , );
LB1_q_b[3]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[3]_PORT_A_address_reg = DFFE(LB1_q_b[3]_PORT_A_address, LB1_q_b[3]_clock_0, , , );
LB1_q_b[3]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[3]_PORT_B_address_reg = DFFE(LB1_q_b[3]_PORT_B_address, LB1_q_b[3]_clock_1, , , );
LB1_q_b[3]_PORT_A_write_enable = GND;
LB1_q_b[3]_PORT_A_write_enable_reg = DFFE(LB1_q_b[3]_PORT_A_write_enable, LB1_q_b[3]_clock_0, , , );
LB1_q_b[3]_PORT_B_write_enable = MB1L2;
LB1_q_b[3]_PORT_B_write_enable_reg = DFFE(LB1_q_b[3]_PORT_B_write_enable, LB1_q_b[3]_clock_1, , , );
LB1_q_b[3]_clock_0 = NB1__clk0;
LB1_q_b[3]_clock_1 = A1L5;
LB1_q_b[3]_PORT_B_data_out = MEMORY(LB1_q_b[3]_PORT_A_data_in_reg, LB1_q_b[3]_PORT_B_data_in_reg, LB1_q_b[3]_PORT_A_address_reg, LB1_q_b[3]_PORT_B_address_reg, LB1_q_b[3]_PORT_A_write_enable_reg, LB1_q_b[3]_PORT_B_write_enable_reg, , , LB1_q_b[3]_clock_0, LB1_q_b[3]_clock_1, , , , );
LB1_q_b[3] = LB1_q_b[3]_PORT_B_data_out[0];


--LB1_q_a[4] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[4]_PORT_A_data_in = VCC;
LB1_q_a[4]_PORT_A_data_in_reg = DFFE(LB1_q_a[4]_PORT_A_data_in, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4]_PORT_B_data_in = MB1_ram_rom_data_reg[4];
LB1_q_a[4]_PORT_B_data_in_reg = DFFE(LB1_q_a[4]_PORT_B_data_in, LB1_q_a[4]_clock_1, , , );
LB1_q_a[4]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[4]_PORT_A_address_reg = DFFE(LB1_q_a[4]_PORT_A_address, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[4]_PORT_B_address_reg = DFFE(LB1_q_a[4]_PORT_B_address, LB1_q_a[4]_clock_1, , , );
LB1_q_a[4]_PORT_A_write_enable = GND;
LB1_q_a[4]_PORT_A_write_enable_reg = DFFE(LB1_q_a[4]_PORT_A_write_enable, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4]_PORT_B_write_enable = MB1L2;
LB1_q_a[4]_PORT_B_write_enable_reg = DFFE(LB1_q_a[4]_PORT_B_write_enable, LB1_q_a[4]_clock_1, , , );
LB1_q_a[4]_clock_0 = NB1__clk0;
LB1_q_a[4]_clock_1 = A1L5;
LB1_q_a[4]_PORT_A_data_out = MEMORY(LB1_q_a[4]_PORT_A_data_in_reg, LB1_q_a[4]_PORT_B_data_in_reg, LB1_q_a[4]_PORT_A_address_reg, LB1_q_a[4]_PORT_B_address_reg, LB1_q_a[4]_PORT_A_write_enable_reg, LB1_q_a[4]_PORT_B_write_enable_reg, , , LB1_q_a[4]_clock_0, LB1_q_a[4]_clock_1, , , , );
LB1_q_a[4] = LB1_q_a[4]_PORT_A_data_out[0];

--LB1_q_b[4] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[4]
LB1_q_b[4]_PORT_A_data_in = VCC;
LB1_q_b[4]_PORT_A_data_in_reg = DFFE(LB1_q_b[4]_PORT_A_data_in, LB1_q_b[4]_clock_0, , , );
LB1_q_b[4]_PORT_B_data_in = MB1_ram_rom_data_reg[4];
LB1_q_b[4]_PORT_B_data_in_reg = DFFE(LB1_q_b[4]_PORT_B_data_in, LB1_q_b[4]_clock_1, , , );
LB1_q_b[4]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[4]_PORT_A_address_reg = DFFE(LB1_q_b[4]_PORT_A_address, LB1_q_b[4]_clock_0, , , );
LB1_q_b[4]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[4]_PORT_B_address_reg = DFFE(LB1_q_b[4]_PORT_B_address, LB1_q_b[4]_clock_1, , , );
LB1_q_b[4]_PORT_A_write_enable = GND;
LB1_q_b[4]_PORT_A_write_enable_reg = DFFE(LB1_q_b[4]_PORT_A_write_enable, LB1_q_b[4]_clock_0, , , );
LB1_q_b[4]_PORT_B_write_enable = MB1L2;
LB1_q_b[4]_PORT_B_write_enable_reg = DFFE(LB1_q_b[4]_PORT_B_write_enable, LB1_q_b[4]_clock_1, , , );
LB1_q_b[4]_clock_0 = NB1__clk0;
LB1_q_b[4]_clock_1 = A1L5;
LB1_q_b[4]_PORT_B_data_out = MEMORY(LB1_q_b[4]_PORT_A_data_in_reg, LB1_q_b[4]_PORT_B_data_in_reg, LB1_q_b[4]_PORT_A_address_reg, LB1_q_b[4]_PORT_B_address_reg, LB1_q_b[4]_PORT_A_write_enable_reg, LB1_q_b[4]_PORT_B_write_enable_reg, , , LB1_q_b[4]_clock_0, LB1_q_b[4]_clock_1, , , , );
LB1_q_b[4] = LB1_q_b[4]_PORT_B_data_out[0];


--LB1_q_a[5] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[5]_PORT_A_data_in = VCC;
LB1_q_a[5]_PORT_A_data_in_reg = DFFE(LB1_q_a[5]_PORT_A_data_in, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5]_PORT_B_data_in = MB1_ram_rom_data_reg[5];
LB1_q_a[5]_PORT_B_data_in_reg = DFFE(LB1_q_a[5]_PORT_B_data_in, LB1_q_a[5]_clock_1, , , );
LB1_q_a[5]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[5]_PORT_A_address_reg = DFFE(LB1_q_a[5]_PORT_A_address, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[5]_PORT_B_address_reg = DFFE(LB1_q_a[5]_PORT_B_address, LB1_q_a[5]_clock_1, , , );
LB1_q_a[5]_PORT_A_write_enable = GND;
LB1_q_a[5]_PORT_A_write_enable_reg = DFFE(LB1_q_a[5]_PORT_A_write_enable, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5]_PORT_B_write_enable = MB1L2;
LB1_q_a[5]_PORT_B_write_enable_reg = DFFE(LB1_q_a[5]_PORT_B_write_enable, LB1_q_a[5]_clock_1, , , );
LB1_q_a[5]_clock_0 = NB1__clk0;
LB1_q_a[5]_clock_1 = A1L5;
LB1_q_a[5]_PORT_A_data_out = MEMORY(LB1_q_a[5]_PORT_A_data_in_reg, LB1_q_a[5]_PORT_B_data_in_reg, LB1_q_a[5]_PORT_A_address_reg, LB1_q_a[5]_PORT_B_address_reg, LB1_q_a[5]_PORT_A_write_enable_reg, LB1_q_a[5]_PORT_B_write_enable_reg, , , LB1_q_a[5]_clock_0, LB1_q_a[5]_clock_1, , , , );
LB1_q_a[5] = LB1_q_a[5]_PORT_A_data_out[0];

--LB1_q_b[5] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[5]
LB1_q_b[5]_PORT_A_data_in = VCC;
LB1_q_b[5]_PORT_A_data_in_reg = DFFE(LB1_q_b[5]_PORT_A_data_in, LB1_q_b[5]_clock_0, , , );
LB1_q_b[5]_PORT_B_data_in = MB1_ram_rom_data_reg[5];
LB1_q_b[5]_PORT_B_data_in_reg = DFFE(LB1_q_b[5]_PORT_B_data_in, LB1_q_b[5]_clock_1, , , );
LB1_q_b[5]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[5]_PORT_A_address_reg = DFFE(LB1_q_b[5]_PORT_A_address, LB1_q_b[5]_clock_0, , , );
LB1_q_b[5]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[5]_PORT_B_address_reg = DFFE(LB1_q_b[5]_PORT_B_address, LB1_q_b[5]_clock_1, , , );
LB1_q_b[5]_PORT_A_write_enable = GND;
LB1_q_b[5]_PORT_A_write_enable_reg = DFFE(LB1_q_b[5]_PORT_A_write_enable, LB1_q_b[5]_clock_0, , , );
LB1_q_b[5]_PORT_B_write_enable = MB1L2;
LB1_q_b[5]_PORT_B_write_enable_reg = DFFE(LB1_q_b[5]_PORT_B_write_enable, LB1_q_b[5]_clock_1, , , );
LB1_q_b[5]_clock_0 = NB1__clk0;
LB1_q_b[5]_clock_1 = A1L5;
LB1_q_b[5]_PORT_B_data_out = MEMORY(LB1_q_b[5]_PORT_A_data_in_reg, LB1_q_b[5]_PORT_B_data_in_reg, LB1_q_b[5]_PORT_A_address_reg, LB1_q_b[5]_PORT_B_address_reg, LB1_q_b[5]_PORT_A_write_enable_reg, LB1_q_b[5]_PORT_B_write_enable_reg, , , LB1_q_b[5]_clock_0, LB1_q_b[5]_clock_1, , , , );
LB1_q_b[5] = LB1_q_b[5]_PORT_B_data_out[0];


--LB1_q_a[6] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[6]_PORT_A_data_in = VCC;
LB1_q_a[6]_PORT_A_data_in_reg = DFFE(LB1_q_a[6]_PORT_A_data_in, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6]_PORT_B_data_in = MB1_ram_rom_data_reg[6];
LB1_q_a[6]_PORT_B_data_in_reg = DFFE(LB1_q_a[6]_PORT_B_data_in, LB1_q_a[6]_clock_1, , , );
LB1_q_a[6]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[6]_PORT_A_address_reg = DFFE(LB1_q_a[6]_PORT_A_address, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[6]_PORT_B_address_reg = DFFE(LB1_q_a[6]_PORT_B_address, LB1_q_a[6]_clock_1, , , );
LB1_q_a[6]_PORT_A_write_enable = GND;
LB1_q_a[6]_PORT_A_write_enable_reg = DFFE(LB1_q_a[6]_PORT_A_write_enable, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6]_PORT_B_write_enable = MB1L2;
LB1_q_a[6]_PORT_B_write_enable_reg = DFFE(LB1_q_a[6]_PORT_B_write_enable, LB1_q_a[6]_clock_1, , , );
LB1_q_a[6]_clock_0 = NB1__clk0;
LB1_q_a[6]_clock_1 = A1L5;
LB1_q_a[6]_PORT_A_data_out = MEMORY(LB1_q_a[6]_PORT_A_data_in_reg, LB1_q_a[6]_PORT_B_data_in_reg, LB1_q_a[6]_PORT_A_address_reg, LB1_q_a[6]_PORT_B_address_reg, LB1_q_a[6]_PORT_A_write_enable_reg, LB1_q_a[6]_PORT_B_write_enable_reg, , , LB1_q_a[6]_clock_0, LB1_q_a[6]_clock_1, , , , );
LB1_q_a[6] = LB1_q_a[6]_PORT_A_data_out[0];

--LB1_q_b[6] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[6]