up3_clock.map.summary

来自「用VHDL语言编写的一个闹钟程序」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sat Jun 09 21:40:56 2007
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : UP3_CLOCK
Top-level Entity Name : UP3_CLOCK
Family : Cyclone
Total logic elements : 405
Total pins : 25
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0