up3_clock.map.rpt

用VHDL语言编写的一个闹钟程序

; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; -1                 ; -1                 ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Maximum Number of M-RAM Memory Blocks                              ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                 ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+
; UP3_CLOCK.vhd                    ; yes             ; User VHDL File  ; H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 405   ;
;     -- Combinational with no register       ; 218   ;
;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 185   ;
;                                             ;       ;