up3_clock.map.rpt

用VHDL语言编写的一个闹钟程序

Analysis & Synthesis report for UP3_CLOCK
Sat Jun 09 21:40:56 2007
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |UP3_CLOCK|state
  8. State Machine - |UP3_CLOCK|next_command
  9. State Machine - |UP3_CLOCK|state1
 10. State Machine - |UP3_CLOCK|next_command1
 11. State Machine - |UP3_CLOCK|state2
 12. State Machine - |UP3_CLOCK|next_command2
 13. Logic Cells Representing Combinational Loops
 14. General Register Statistics
 15. Inverted Register Statistics
 16. Multiplexer Restructuring Statistics (Restructuring Performed)
 17. Analysis & Synthesis Equations
 18. Analysis & Synthesis Messages



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; Legal Notice ;
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Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.