up3_clock.map.qmsg

用VHDL语言编写的一个闹钟程序

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TIME UP3_CLOCK.vhd(603) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(603): signal \"TIME\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 603 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET_ALARM UP3_CLOCK.vhd(604) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(604): signal \"SET_ALARM\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 604 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TIME UP3_CLOCK.vhd(606) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(606): signal \"TIME\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 606 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GIVE_TIME UP3_CLOCK.vhd(616) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(616): signal \"GIVE_TIME\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 616 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_SECD1 UP3_CLOCK.vhd(617) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(617): signal \"BCD_SECD1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 617 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_SECD0 UP3_CLOCK.vhd(618) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(618): signal \"BCD_SECD0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 618 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_MIND1 UP3_CLOCK.vhd(619) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(619): signal \"BCD_MIND1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 619 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_MIND0 UP3_CLOCK.vhd(620) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(620): signal \"BCD_MIND0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 620 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "LCD_RW~reg0 data_in GND " "Warning: Reduced register \"LCD_RW~reg0\" with stuck data_in port to stuck value GND" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 10 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|UP3_CLOCK\|state 41 " "Info: State machine \"\|UP3_CLOCK\|state\" contains 41 states" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|UP3_CLOCK\|next_command 41 " "Info: State machine \"\|UP3_CLOCK\|next_command\" contains 41 states" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}