up3_clock.map.qmsg

用VHDL语言编写的一个闹钟程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 21:40:46 2007 " "Info: Processing started: Sat Jun 09 21:40:46 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UP3_CLOCK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UP3_CLOCK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UP3_CLOCK-a " "Info: Found design unit 1: UP3_CLOCK-a" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 UP3_CLOCK " "Info: Found entity 1: UP3_CLOCK" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UP3_CLOCK " "Info: Elaborating entity \"UP3_CLOCK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "BCD_YEAR1 UP3_CLOCK.vhd(35) " "Warning (10541): VHDL Signal Declaration warning at UP3_CLOCK.vhd(35): used implicit default value for signal \"BCD_YEAR1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 35 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "BCD_YEAR0 UP3_CLOCK.vhd(35) " "Warning (10541): VHDL Signal Declaration warning at UP3_CLOCK.vhd(35): used implicit default value for signal \"BCD_YEAR0\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 35 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "BCD_MONTH1 UP3_CLOCK.vhd(35) " "Warning (10541): VHDL Signal Declaration warning at UP3_CLOCK.vhd(35): used implicit default value for signal \"BCD_MONTH1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 35 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "BCD_MONTH0 UP3_CLOCK.vhd(35) " "Warning (10541): VHDL Signal Declaration warning at UP3_CLOCK.vhd(35): used implicit default value for signal \"BCD_MONTH0\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 35 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "BCD_DAY1 UP3_CLOCK.vhd(35) " "Warning (10541): VHDL Signal Declaration warning at UP3_CLOCK.vhd(35): used implicit default value for signal \"BCD_DAY1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 35 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ALARM_LABEL UP3_CLOCK.vhd(38) " "Info (10035): Verilog HDL or VHDL information at UP3_CLOCK.vhd(38): object \"ALARM_LABEL\" declared but not used" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 38 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}