up3_clock.sim.qmsg

用VHDL语言编写的一个闹钟程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 21:50:20 2007 " "Info: Processing started: Sat Jun 09 21:50:20 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISIM_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" {  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command.hold " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command.hold\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command.reset1 " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command.reset1\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command.toggle_e " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command.toggle_e\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command1.toggle_e1 " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command1.toggle_e1\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command1.hold1 " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command1.hold1\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command2.toggle_e2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command2.toggle_e2\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 631 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|UP3_CLOCK\|next_command2.hold2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|UP3_CLOCK\|next_command2.hold2\" was synthesized away" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 631 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Info" "ISIM_SIM_END_TIME_LESS_CHANNEL_END" "2.0 ns 1.0 us " "Info: Simulation end time 2.0 ns did not reach the end of the input vector, which ended at 1.0 us" {  } {  } 0 0 "Simulation end time %1!s! did not reach the end of the input vector, which ended at %2!s!" 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "BCD_SECD1\[3\] " "Warning: Compiler packed, optimized or synthesized away node \"BCD_SECD1\[3\]\". Ignored vector source file node." {  } { { "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vwf" "" { Waveform "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vwf" "BCD_SECD1\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "BCD_MIND1\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"BCD_MIND1\[3\]\" in design." {  } { { "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vwf" "" { Waveform "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vwf" "BCD_MIND1\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|CLOSE_ALARM " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|CLOSE_ALARM\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|SET_ALARM " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|SET_ALARM\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|GIVE_TIME " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|GIVE_TIME\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|SET_MOD " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|SET_MOD\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|SET_CHANGE " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|SET_CHANGE\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|SET_TIME " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|SET_TIME\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|SET_ADD " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|SET_ADD\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|UP3_CLOCK\|ALARM " "Warning: Can't find signal in vector source file for input pin \"\|UP3_CLOCK\|ALARM\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      0.00 % " "Info: Simulation coverage is       0.00 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "0 " "Info: Number of transitions in simulation is 0" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 17 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 09 21:50:21 2007 " "Info: Processing ended: Sat Jun 09 21:50:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}