up3_clock.tan.qmsg

来自「用VHDL语言编写的一个闹钟程序」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Warning" "WTAN_SCC_LOOP_TOO_BIG" "131 " "Warning: Design contains combinational loop of 131 nodes. Estimating the delays through the loop." {  } {  } 0 0 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_48Mhz " "Info: Assuming node \"clk_48Mhz\" is an undefined clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/学习/EDA技术应用/EDA/实验三－电子表/最终版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_48Mhz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}