up3_clock.fit.summary

来自「用VHDL语言编写的一个闹钟程序」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Sat Jun 09 21:41:06 2007
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : UP3_CLOCK
Top-level Entity Name : UP3_CLOCK
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 403 / 5,980 ( 7 % )
Total pins : 25 / 185 ( 14 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )