display.fit.qmsg

用 vhdl 语言编写的1602的小程序

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.692 ns register register " "Info: Estimated most critical path is register to register delay of 5.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_COUNT_400HZ\[5\] 1 REG LAB_X2_Y5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.590 ns) 1.446 ns LessThan~412 2 COMB LAB_X3_Y4 1 " "Info: 2: + IC(0.856 ns) + CELL(0.590 ns) = 1.446 ns; Loc. = LAB_X3_Y4; Fanout = 1; COMB Node = 'LessThan~412'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.446 ns" { CLK_COUNT_400HZ[5] LessThan~412 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 2.110 ns LessThan~413 3 COMB LAB_X3_Y4 1 " "Info: 3: + IC(0.074 ns) + CELL(0.590 ns) = 2.110 ns; Loc. = LAB_X3_Y4; Fanout = 1; COMB Node = 'LessThan~413'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "0.664 ns" { LessThan~412 LessThan~413 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.442 ns) 2.774 ns LessThan~415 4 COMB LAB_X3_Y4 2 " "Info: 4: + IC(0.222 ns) + CELL(0.442 ns) = 2.774 ns; Loc. = LAB_X3_Y4; Fanout = 2; COMB Node = 'LessThan~415'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "0.664 ns" { LessThan~413 LessThan~415 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 3.438 ns CLK_COUNT_400HZ\[19\]~396 5 COMB LAB_X3_Y4 20 " "Info: 5: + IC(0.074 ns) + CELL(0.590 ns) = 3.438 ns; Loc. = LAB_X3_Y4; Fanout = 20; COMB Node = 'CLK_COUNT_400HZ\[19\]~396'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "0.664 ns" { LessThan~415 CLK_COUNT_400HZ[19]~396 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.142 ns) + CELL(1.112 ns) 5.692 ns CLK_COUNT_400HZ\[5\] 6 REG LAB_X2_Y5 4 " "Info: 6: + IC(1.142 ns) + CELL(1.112 ns) = 5.692 ns; Loc. = LAB_X2_Y5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.254 ns" { CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.324 ns ( 58.40 % ) " "Info: Total cell delay = 3.324 ns ( 58.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.368 ns ( 41.60 % ) " "Info: Total interconnect delay = 2.368 ns ( 41.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.692 ns" { CLK_COUNT_400HZ[5] LessThan~412 LessThan~413 LessThan~415 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[0\] a permanently enabled " "Info: Pin DATA_BUS\[0\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[0\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[0] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[1\] a permanently enabled " "Info: Pin DATA_BUS\[1\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[1\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[1] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[2\] a permanently enabled " "Info: Pin DATA_BUS\[2\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[2\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[2] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[3\] a permanently enabled " "Info: Pin DATA_BUS\[3\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[3\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[3] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[4\] a permanently enabled " "Info: Pin DATA_BUS\[4\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[4\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[4] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[5\] a permanently enabled " "Info: Pin DATA_BUS\[5\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[5\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[5] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[6\] a permanently enabled " "Info: Pin DATA_BUS\[6\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[6\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[6] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[7\] a permanently enabled " "Info: Pin DATA_BUS\[7\] has a permanently enabled output enable" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[7\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DATA_BUS[7] } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { LCD_RW } "NODE_NAME" } "" } } { "H:/FPGA/DISPLAY/DISPLAY.fld" "" { Floorplan "H:/FPGA/DISPLAY/DISPLAY.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 29 22:51:57 2007 " "Info: Processing ended: Wed Aug 29 22:51:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}