display.tan.qmsg

用 vhdl 语言编写的1602的小程序

{ "Info" "ITDB_TH_RESULT" "next_command.write3_char1 DS0 CLK 0.260 ns register " "Info: th for register \"next_command.write3_char1\" (data pin = \"DS0\", clock pin = \"CLK\") is 0.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.606 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 8.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns CLK_400HZ 2 REG LC_X3_Y4_N8 66 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X3_Y4_N8; Fanout = 66; REG Node = 'CLK_400HZ'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.658 ns" { CLK CLK_400HZ } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.711 ns) 8.606 ns next_command.write3_char1 3 REG LC_X11_Y6_N7 2 " "Info: 3: + IC(4.768 ns) + CELL(0.711 ns) = 8.606 ns; Loc. = LC_X11_Y6_N7; Fanout = 2; REG Node = 'next_command.write3_char1'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.479 ns" { CLK_400HZ next_command.write3_char1 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.20 % ) " "Info: Total cell delay = 3.115 ns ( 36.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.491 ns ( 63.80 % ) " "Info: Total interconnect delay = 5.491 ns ( 63.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.606 ns" { CLK CLK_400HZ next_command.write3_char1 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.606 ns" { CLK CLK~out0 CLK_400HZ next_command.write3_char1 } { 0.000ns 0.000ns 0.723ns 4.768ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.361 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DS0 1 PIN PIN_58 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 'DS0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { DS0 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.154 ns) + CELL(0.738 ns) 8.361 ns next_command.write3_char1 2 REG LC_X11_Y6_N7 2 " "Info: 2: + IC(6.154 ns) + CELL(0.738 ns) = 8.361 ns; Loc. = LC_X11_Y6_N7; Fanout = 2; REG Node = 'next_command.write3_char1'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "6.892 ns" { DS0 next_command.write3_char1 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 26.40 % ) " "Info: Total cell delay = 2.207 ns ( 26.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.154 ns ( 73.60 % ) " "Info: Total interconnect delay = 6.154 ns ( 73.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.361 ns" { DS0 next_command.write3_char1 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.361 ns" { DS0 DS0~out0 next_command.write3_char1 } { 0.000ns 0.000ns 6.154ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.606 ns" { CLK CLK_400HZ next_command.write3_char1 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.606 ns" { CLK CLK~out0 CLK_400HZ next_command.write3_char1 } { 0.000ns 0.000ns 0.723ns 4.768ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.361 ns" { DS0 next_command.write3_char1 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.361 ns" { DS0 DS0~out0 next_command.write3_char1 } { 0.000ns 0.000ns 6.154ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 29 22:52:02 2007 " "Info: Processing ended: Wed Aug 29 22:52:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}