display.tan.qmsg

用 vhdl 语言编写的1602的小程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 37 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CLK_COUNT_400HZ\[6\] register CLK_COUNT_400HZ\[0\] 137.78 MHz 7.258 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 137.78 MHz between source register \"CLK_COUNT_400HZ\[6\]\" and destination register \"CLK_COUNT_400HZ\[0\]\" (period= 7.258 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.997 ns + Longest register register " "Info: + Longest register to register delay is 6.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_COUNT_400HZ\[6\] 1 REG LC_X2_Y5_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y5_N6; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[6\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK_COUNT_400HZ[6] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.590 ns) 1.853 ns LessThan~412 2 COMB LC_X3_Y4_N2 1 " "Info: 2: + IC(1.263 ns) + CELL(0.590 ns) = 1.853 ns; Loc. = LC_X3_Y4_N2; Fanout = 1; COMB Node = 'LessThan~412'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.853 ns" { CLK_COUNT_400HZ[6] LessThan~412 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.590 ns) 2.878 ns LessThan~413 3 COMB LC_X3_Y4_N9 1 " "Info: 3: + IC(0.435 ns) + CELL(0.590 ns) = 2.878 ns; Loc. = LC_X3_Y4_N9; Fanout = 1; COMB Node = 'LessThan~413'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.025 ns" { LessThan~412 LessThan~413 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.590 ns) 3.901 ns LessThan~415 4 COMB LC_X3_Y4_N7 2 " "Info: 4: + IC(0.433 ns) + CELL(0.590 ns) = 3.901 ns; Loc. = LC_X3_Y4_N7; Fanout = 2; COMB Node = 'LessThan~415'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.023 ns" { LessThan~413 LessThan~415 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 4.641 ns CLK_COUNT_400HZ\[19\]~396 5 COMB LC_X3_Y4_N6 20 " "Info: 5: + IC(0.448 ns) + CELL(0.292 ns) = 4.641 ns; Loc. = LC_X3_Y4_N6; Fanout = 20; COMB Node = 'CLK_COUNT_400HZ\[19\]~396'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "0.740 ns" { LessThan~415 CLK_COUNT_400HZ[19]~396 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(1.112 ns) 6.997 ns CLK_COUNT_400HZ\[0\] 6 REG LC_X2_Y5_N0 3 " "Info: 6: + IC(1.244 ns) + CELL(1.112 ns) = 6.997 ns; Loc. = LC_X2_Y5_N0; Fanout = 3; REG Node = 'CLK_COUNT_400HZ\[0\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.356 ns" { CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.174 ns ( 45.36 % ) " "Info: Total cell delay = 3.174 ns ( 45.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.823 ns ( 54.64 % ) " "Info: Total interconnect delay = 3.823 ns ( 54.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "6.997 ns" { CLK_COUNT_400HZ[6] LessThan~412 LessThan~413 LessThan~415 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "6.997 ns" { CLK_COUNT_400HZ[6] LessThan~412 LessThan~413 LessThan~415 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[0] } { 0.000ns 1.263ns 0.435ns 0.433ns 0.448ns 1.244ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns CLK_COUNT_400HZ\[0\] 2 REG LC_X2_Y5_N0 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X2_Y5_N0; Fanout = 3; REG Node = 'CLK_COUNT_400HZ\[0\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.434 ns" { CLK CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns CLK_COUNT_400HZ\[6\] 2 REG LC_X2_Y5_N6 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X2_Y5_N6; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[6\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.434 ns" { CLK CLK_COUNT_400HZ[6] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[6] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[6] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[6] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[6] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "6.997 ns" { CLK_COUNT_400HZ[6] LessThan~412 LessThan~413 LessThan~415 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "6.997 ns" { CLK_COUNT_400HZ[6] LessThan~412 LessThan~413 LessThan~415 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[0] } { 0.000ns 1.263ns 0.435ns 0.433ns 0.448ns 1.244ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.292ns 1.112ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[6] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[6] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "CLK_COUNT_400HZ\[5\] RES CLK 8.168 ns register " "Info: tsu for register \"CLK_COUNT_400HZ\[5\]\" (data pin = \"RES\", clock pin = \"CLK\") is 8.168 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.034 ns + Longest pin register " "Info: + Longest pin to register delay is 11.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RES 1 PIN PIN_60 67 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_60; Fanout = 67; PIN Node = 'RES'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { RES } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.619 ns) + CELL(0.590 ns) 8.678 ns CLK_COUNT_400HZ\[19\]~396 2 COMB LC_X3_Y4_N6 20 " "Info: 2: + IC(6.619 ns) + CELL(0.590 ns) = 8.678 ns; Loc. = LC_X3_Y4_N6; Fanout = 20; COMB Node = 'CLK_COUNT_400HZ\[19\]~396'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "7.209 ns" { RES CLK_COUNT_400HZ[19]~396 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(1.112 ns) 11.034 ns CLK_COUNT_400HZ\[5\] 3 REG LC_X2_Y5_N5 4 " "Info: 3: + IC(1.244 ns) + CELL(1.112 ns) = 11.034 ns; Loc. = LC_X2_Y5_N5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.356 ns" { CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.171 ns ( 28.74 % ) " "Info: Total cell delay = 3.171 ns ( 28.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.863 ns ( 71.26 % ) " "Info: Total interconnect delay = 7.863 ns ( 71.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "11.034 ns" { RES CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "11.034 ns" { RES RES~out0 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 6.619ns 1.244ns } { 0.000ns 1.469ns 0.590ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns CLK_COUNT_400HZ\[5\] 2 REG LC_X2_Y5_N5 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X2_Y5_N5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.434 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "11.034 ns" { RES CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "11.034 ns" { RES RES~out0 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 6.619ns 1.244ns } { 0.000ns 1.469ns 0.590ns 1.112ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "2.903 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LCD_RS LCD_RS~reg0 14.246 ns register " "Info: tco from clock \"CLK\" to destination pin \"LCD_RS\" through register \"LCD_RS~reg0\" is 14.246 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.606 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 8.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { CLK } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns CLK_400HZ 2 REG LC_X3_Y4_N8 66 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X3_Y4_N8; Fanout = 66; REG Node = 'CLK_400HZ'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "1.658 ns" { CLK CLK_400HZ } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.711 ns) 8.606 ns LCD_RS~reg0 3 REG LC_X14_Y7_N3 2 " "Info: 3: + IC(4.768 ns) + CELL(0.711 ns) = 8.606 ns; Loc. = LC_X14_Y7_N3; Fanout = 2; REG Node = 'LCD_RS~reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.479 ns" { CLK_400HZ LCD_RS~reg0 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.20 % ) " "Info: Total cell delay = 3.115 ns ( 36.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.491 ns ( 63.80 % ) " "Info: Total interconnect delay = 5.491 ns ( 63.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.606 ns" { CLK CLK_400HZ LCD_RS~reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.606 ns" { CLK CLK~out0 CLK_400HZ LCD_RS~reg0 } { 0.000ns 0.000ns 0.723ns 4.768ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.416 ns + Longest register pin " "Info: + Longest register to pin delay is 5.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_RS~reg0 1 REG LC_X14_Y7_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y7_N3; Fanout = 2; REG Node = 'LCD_RS~reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "" { LCD_RS~reg0 } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.308 ns) + CELL(2.108 ns) 5.416 ns LCD_RS 2 PIN PIN_108 0 " "Info: 2: + IC(3.308 ns) + CELL(2.108 ns) = 5.416 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'LCD_RS'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.416 ns" { LCD_RS~reg0 LCD_RS } "NODE_NAME" } "" } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 38.92 % ) " "Info: Total cell delay = 2.108 ns ( 38.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.308 ns ( 61.08 % ) " "Info: Total interconnect delay = 3.308 ns ( 61.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.416 ns" { LCD_RS~reg0 LCD_RS } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.416 ns" { LCD_RS~reg0 LCD_RS } { 0.000ns 3.308ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "8.606 ns" { CLK CLK_400HZ LCD_RS~reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "8.606 ns" { CLK CLK~out0 CLK_400HZ LCD_RS~reg0 } { 0.000ns 0.000ns 0.723ns 4.768ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DISPLAY" "UNKNOWN" "V1" "H:/FPGA/DISPLAY/db/DISPLAY.quartus_db" { Floorplan "H:/FPGA/DISPLAY/" "" "5.416 ns" { LCD_RS~reg0 LCD_RS } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.416 ns" { LCD_RS~reg0 LCD_RS } { 0.000ns 3.308ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}