display.map.qmsg

用 vhdl 语言编写的1602的小程序

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "next_command.hold data_in GND " "Warning: Reduced register \"next_command.hold\" with stuck data_in port to stuck value GND" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~15 " "Warning: Node \"DATA_BUS~15\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~14 " "Warning: Node \"DATA_BUS~14\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~13 " "Warning: Node \"DATA_BUS~13\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~12 " "Warning: Node \"DATA_BUS~12\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~11 " "Warning: Node \"DATA_BUS~11\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~10 " "Warning: Node \"DATA_BUS~10\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~9 " "Warning: Node \"DATA_BUS~9\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS~8 " "Warning: Node \"DATA_BUS~8\"" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_RW GND " "Warning: Pin \"LCD_RW\" stuck at GND" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 11 -1 0 } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "126 " "Info: Implemented 126 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "111 " "Info: Implemented 111 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 29 22:51:51 2007 " "Info: Processing ended: Wed Aug 29 22:51:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}