📄 display.map.qmsg
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{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DISPLAY\|next_command 29 " "Info: State machine \"\|DISPLAY\|next_command\" contains 29 states" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } } } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DISPLAY\|state " "Info: Selected Auto state machine encoding method for state machine \"\|DISPLAY\|state\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } } } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DISPLAY\|state " "Info: Encoding result for state machine \"\|DISPLAY\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "29 " "Info: Completed encoding using 29 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.display_clear " "Info: Encoded state bit \"state.display_clear\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.display_off " "Info: Encoded state bit \"state.display_off\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.reset3 " "Info: Encoded state bit \"state.reset3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.goto_nextline " "Info: Encoded state bit \"state.goto_nextline\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.reset2 " "Info: Encoded state bit \"state.reset2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.hold " "Info: Encoded state bit \"state.hold\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.toggle_e " "Info: Encoded state bit \"state.toggle_e\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.return_home " "Info: Encoded state bit \"state.return_home\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.display_set " "Info: Encoded state bit \"state.display_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write3_char3 " "Info: Encoded state bit \"state.write3_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write3_char2 " "Info: Encoded state bit \"state.write3_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write3_char1 " "Info: Encoded state bit \"state.write3_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write2_char3 " "Info: Encoded state bit \"state.write2_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write2_char2 " "Info: Encoded state bit \"state.write2_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write2_char1 " "Info: Encoded state bit \"state.write2_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write1_char3 " "Info: Encoded state bit \"state.write1_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write1_char2 " "Info: Encoded state bit \"state.write1_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write1_char1 " "Info: Encoded state bit \"state.write1_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char7 " "Info: Encoded state bit \"state.write_char7\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char6 " "Info: Encoded state bit \"state.write_char6\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char5 " "Info: Encoded state bit \"state.write_char5\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char4 " "Info: Encoded state bit \"state.write_char4\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char3 " "Info: Encoded state bit \"state.write_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char2 " "Info: Encoded state bit \"state.write_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.write_char1 " "Info: Encoded state bit \"state.write_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.mode_set " "Info: Encoded state bit \"state.mode_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.display_on " "Info: Encoded state bit \"state.display_on\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.func_set " "Info: Encoded state bit \"state.func_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.reset1 " "Info: Encoded state bit \"state.reset1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} } { } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.reset1 00000000000000000000000000000 " "Info: State \"\|DISPLAY\|state.reset1\" uses code string \"00000000000000000000000000000\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.func_set 00000000000000000000000000011 " "Info: State \"\|DISPLAY\|state.func_set\" uses code string \"00000000000000000000000000011\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.display_on 00000000000000000000000000101 " "Info: State \"\|DISPLAY\|state.display_on\" uses code string \"00000000000000000000000000101\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.mode_set 00000000000000000000000001001 " "Info: State \"\|DISPLAY\|state.mode_set\" uses code string \"00000000000000000000000001001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char1 00000000000000000000000010001 " "Info: State \"\|DISPLAY\|state.write_char1\" uses code string \"00000000000000000000000010001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char2 00000000000000000000000100001 " "Info: State \"\|DISPLAY\|state.write_char2\" uses code string \"00000000000000000000000100001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char3 00000000000000000000001000001 " "Info: State \"\|DISPLAY\|state.write_char3\" uses code string \"00000000000000000000001000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char4 00000000000000000000010000001 " "Info: State \"\|DISPLAY\|state.write_char4\" uses code string \"00000000000000000000010000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char5 00000000000000000000100000001 " "Info: State \"\|DISPLAY\|state.write_char5\" uses code string \"00000000000000000000100000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char6 00000000000000000001000000001 " "Info: State \"\|DISPLAY\|state.write_char6\" uses code string \"00000000000000000001000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write_char7 00000000000000000010000000001 " "Info: State \"\|DISPLAY\|state.write_char7\" uses code string \"00000000000000000010000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write1_char1 00000000000000000100000000001 " "Info: State \"\|DISPLAY\|state.write1_char1\" uses code string \"00000000000000000100000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write1_char2 00000000000000001000000000001 " "Info: State \"\|DISPLAY\|state.write1_char2\" uses code string \"00000000000000001000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write1_char3 00000000000000010000000000001 " "Info: State \"\|DISPLAY\|state.write1_char3\" uses code string \"00000000000000010000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write2_char1 00000000000000100000000000001 " "Info: State \"\|DISPLAY\|state.write2_char1\" uses code string \"00000000000000100000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write2_char2 00000000000001000000000000001 " "Info: State \"\|DISPLAY\|state.write2_char2\" uses code string \"00000000000001000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write2_char3 00000000000010000000000000001 " "Info: State \"\|DISPLAY\|state.write2_char3\" uses code string \"00000000000010000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write3_char1 00000000000100000000000000001 " "Info: State \"\|DISPLAY\|state.write3_char1\" uses code string \"00000000000100000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write3_char2 00000000001000000000000000001 " "Info: State \"\|DISPLAY\|state.write3_char2\" uses code string \"00000000001000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.write3_char3 00000000010000000000000000001 " "Info: State \"\|DISPLAY\|state.write3_char3\" uses code string \"00000000010000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.display_set 00000000100000000000000000001 " "Info: State \"\|DISPLAY\|state.display_set\" uses code string \"00000000100000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.return_home 00000001000000000000000000001 " "Info: State \"\|DISPLAY\|state.return_home\" uses code string \"00000001000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.toggle_e 00000010000000000000000000001 " "Info: State \"\|DISPLAY\|state.toggle_e\" uses code string \"00000010000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.hold 00000100000000000000000000001 " "Info: State \"\|DISPLAY\|state.hold\" uses code string \"00000100000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.reset2 00001000000000000000000000001 " "Info: State \"\|DISPLAY\|state.reset2\" uses code string \"00001000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.goto_nextline 00010000000000000000000000001 " "Info: State \"\|DISPLAY\|state.goto_nextline\" uses code string \"00010000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.reset3 00100000000000000000000000001 " "Info: State \"\|DISPLAY\|state.reset3\" uses code string \"00100000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.display_off 01000000000000000000000000001 " "Info: State \"\|DISPLAY\|state.display_off\" uses code string \"01000000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|state.display_clear 10000000000000000000000000001 " "Info: State \"\|DISPLAY\|state.display_clear\" uses code string \"10000000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } } } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DISPLAY\|next_command " "Info: Selected Auto state machine encoding method for state machine \"\|DISPLAY\|next_command\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } } } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DISPLAY\|next_command " "Info: Encoding result for state machine \"\|DISPLAY\|next_command\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "29 " "Info: Completed encoding using 29 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.display_clear " "Info: Encoded state bit \"next_command.display_clear\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.display_off " "Info: Encoded state bit \"next_command.display_off\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.reset3 " "Info: Encoded state bit \"next_command.reset3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.goto_nextline " "Info: Encoded state bit \"next_command.goto_nextline\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.hold " "Info: Encoded state bit \"next_command.hold\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.reset1 " "Info: Encoded state bit \"next_command.reset1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.toggle_e " "Info: Encoded state bit \"next_command.toggle_e\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.return_home " "Info: Encoded state bit \"next_command.return_home\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.display_set " "Info: Encoded state bit \"next_command.display_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write3_char3 " "Info: Encoded state bit \"next_command.write3_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write3_char2 " "Info: Encoded state bit \"next_command.write3_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write3_char1 " "Info: Encoded state bit \"next_command.write3_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write2_char3 " "Info: Encoded state bit \"next_command.write2_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write2_char2 " "Info: Encoded state bit \"next_command.write2_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write2_char1 " "Info: Encoded state bit \"next_command.write2_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write1_char3 " "Info: Encoded state bit \"next_command.write1_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write1_char2 " "Info: Encoded state bit \"next_command.write1_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write1_char1 " "Info: Encoded state bit \"next_command.write1_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char7 " "Info: Encoded state bit \"next_command.write_char7\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char6 " "Info: Encoded state bit \"next_command.write_char6\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char5 " "Info: Encoded state bit \"next_command.write_char5\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char4 " "Info: Encoded state bit \"next_command.write_char4\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char3 " "Info: Encoded state bit \"next_command.write_char3\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char2 " "Info: Encoded state bit \"next_command.write_char2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.write_char1 " "Info: Encoded state bit \"next_command.write_char1\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.mode_set " "Info: Encoded state bit \"next_command.mode_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.display_on " "Info: Encoded state bit \"next_command.display_on\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.func_set " "Info: Encoded state bit \"next_command.func_set\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "next_command.reset2 " "Info: Encoded state bit \"next_command.reset2\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0} } { } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.reset2 00000000000000000000000000000 " "Info: State \"\|DISPLAY\|next_command.reset2\" uses code string \"00000000000000000000000000000\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.func_set 00000000000000000000000000011 " "Info: State \"\|DISPLAY\|next_command.func_set\" uses code string \"00000000000000000000000000011\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.display_on 00000000000000000000000000101 " "Info: State \"\|DISPLAY\|next_command.display_on\" uses code string \"00000000000000000000000000101\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.mode_set 00000000000000000000000001001 " "Info: State \"\|DISPLAY\|next_command.mode_set\" uses code string \"00000000000000000000000001001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char1 00000000000000000000000010001 " "Info: State \"\|DISPLAY\|next_command.write_char1\" uses code string \"00000000000000000000000010001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char2 00000000000000000000000100001 " "Info: State \"\|DISPLAY\|next_command.write_char2\" uses code string \"00000000000000000000000100001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char3 00000000000000000000001000001 " "Info: State \"\|DISPLAY\|next_command.write_char3\" uses code string \"00000000000000000000001000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char4 00000000000000000000010000001 " "Info: State \"\|DISPLAY\|next_command.write_char4\" uses code string \"00000000000000000000010000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char5 00000000000000000000100000001 " "Info: State \"\|DISPLAY\|next_command.write_char5\" uses code string \"00000000000000000000100000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char6 00000000000000000001000000001 " "Info: State \"\|DISPLAY\|next_command.write_char6\" uses code string \"00000000000000000001000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write_char7 00000000000000000010000000001 " "Info: State \"\|DISPLAY\|next_command.write_char7\" uses code string \"00000000000000000010000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write1_char1 00000000000000000100000000001 " "Info: State \"\|DISPLAY\|next_command.write1_char1\" uses code string \"00000000000000000100000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write1_char2 00000000000000001000000000001 " "Info: State \"\|DISPLAY\|next_command.write1_char2\" uses code string \"00000000000000001000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write1_char3 00000000000000010000000000001 " "Info: State \"\|DISPLAY\|next_command.write1_char3\" uses code string \"00000000000000010000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write2_char1 00000000000000100000000000001 " "Info: State \"\|DISPLAY\|next_command.write2_char1\" uses code string \"00000000000000100000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write2_char2 00000000000001000000000000001 " "Info: State \"\|DISPLAY\|next_command.write2_char2\" uses code string \"00000000000001000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write2_char3 00000000000010000000000000001 " "Info: State \"\|DISPLAY\|next_command.write2_char3\" uses code string \"00000000000010000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write3_char1 00000000000100000000000000001 " "Info: State \"\|DISPLAY\|next_command.write3_char1\" uses code string \"00000000000100000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write3_char2 00000000001000000000000000001 " "Info: State \"\|DISPLAY\|next_command.write3_char2\" uses code string \"00000000001000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.write3_char3 00000000010000000000000000001 " "Info: State \"\|DISPLAY\|next_command.write3_char3\" uses code string \"00000000010000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.display_set 00000000100000000000000000001 " "Info: State \"\|DISPLAY\|next_command.display_set\" uses code string \"00000000100000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.return_home 00000001000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.return_home\" uses code string \"00000001000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.toggle_e 00000010000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.toggle_e\" uses code string \"00000010000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.reset1 00000100000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.reset1\" uses code string \"00000100000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.hold 00001000000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.hold\" uses code string \"00001000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.goto_nextline 00010000000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.goto_nextline\" uses code string \"00010000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.reset3 00100000000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.reset3\" uses code string \"00100000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.display_off 01000000000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.display_off\" uses code string \"01000000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DISPLAY\|next_command.display_clear 10000000000000000000000000001 " "Info: State \"\|DISPLAY\|next_command.display_clear\" uses code string \"10000000000000000000000000001\"" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } } } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "next_command.reset1 data_in GND " "Warning: Reduced register \"next_command.reset1\" with stuck data_in port to stuck value GND" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "next_command.toggle_e data_in GND " "Warning: Reduced register \"next_command.toggle_e\" with stuck data_in port to stuck value GND" { } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 61 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
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