display.map.qmsg

来自「用 vhdl 语言编写的1602的小程序」· QMSG 代码 · 共 21 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 29 22:51:48 2007 " "Info: Processing started: Wed Aug 29 22:51:48 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DISPLAY -c DISPLAY " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DISPLAY -c DISPLAY" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DISPLAY.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DISPLAY.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DISPLAY-behav " "Info: Found design unit 1: DISPLAY-behav" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY " "Info: Found entity 1: DISPLAY" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DISPLAY " "Info: Elaborating entity \"DISPLAY\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "LCD_RW~reg0 data_in GND " "Warning: Reduced register \"LCD_RW~reg0\" with stuck data_in port to stuck value GND" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 12 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DISPLAY\|state 29 " "Info: State machine \"\|DISPLAY\|state\" contains 29 states" {  } { { "DISPLAY.vhd" "" { Text "H:/FPGA/DISPLAY/DISPLAY.vhd" 34 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}