display.fit.rpt

用 vhdl 语言编写的1602的小程序

; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve ASDO pin after configuration.        ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in H:/FPGA/DISPLAY/DISPLAY.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in H:/FPGA/DISPLAY/DISPLAY.pin.


+-------------------------------------------------------------------+
; Fitter Resource Usage Summary                                     ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 110 / 5,980 ( 2 % ) ;
;     -- Combinational with no register       ; 24                  ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 86                  ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 50                  ;
;     -- 3 input functions                    ; 7                   ;
;     -- 2 input functions                    ; 51                  ;
;     -- 1 input functions                    ; 1                   ;
;     -- 0 input functions                    ; 1                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 91                  ;
;     -- arithmetic mode                      ; 19                  ;
;     -- qfbk mode                            ; 1                   ;
;     -- register cascade mode                ; 0                   ;
;     -- synchronous clear/load mode          ; 21                  ;
;     -- asynchronous clear/load mode         ; 65                  ;
;                                             ;                     ;
; Total LABs                                  ; 12 / 598 ( 2 % )    ;
; Logic elements in carry chains              ; 20                  ;
; User inserted logic elements                ; 0                   ;
; Virtual pins                                ; 0                   ;
; I/O pins                                    ; 15 / 185 ( 8 % )    ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )      ;
; Global signals                              ; 3                   ;
; M4Ks                                        ; 0 / 20 ( 0 % )      ;
; Total memory bits                           ; 0 / 92,160 ( 0 % )  ;
; Total RAM block bits                        ; 0 / 92,160 ( 0 % )  ;
; PLLs                                        ; 0 / 2 ( 0 % )       ;
; Global clocks                               ; 3 / 8 ( 38 % )      ;
; Maximum fan-out node                        ; RES                 ;
; Maximum fan-out                             ; 67                  ;
; Highest non-global fan-out signal           ; state.hold          ;
; Highest non-global fan-out                  ; 52                  ;
; Total fan-out                               ; 517                 ;
; Average fan-out                             ; 4.07                ;
+---------------------------------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+