top5_rx.v

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

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//  Xilinx, Inc. 2006                 www.xilinx.com
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//  XAPP 485 - 1:7 LVDS in Spartan3E Devices
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//  File name :       top5_rx.v
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//  Description :     Example top level module for using a 5-bit receiver in Spartan 3E
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//  Date - revision : November 1st 2005 - v 1.3
//			Version 1.1 - Initial release with app note
//			Version 1.2 - Inversion mask added, IDDR2s all bought up to top level
//			Version 1.3 - Auto phase aligner added, see inline notes for removing 
//				      this function if its is not required
//
//  Author :          NJS
//
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