serdes_5b_1to7.v

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

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//
//  Xilinx, Inc. 2006                 www.xilinx.com
//
//  XAPP 485 - 7:1 LVDS in Spartan3E Devices
//
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//
//  File name :       serdes_5b_1to7.v
//
//  Description :     5-bit generic 7:1 serdes receiver macro for Spartan 3E
// 			Takes in 5 bits DDR and deserialises this to 35 bits
// 			relies very heavily on component instantiation to allow RLOCing in the code
//
// 			data is received LSBs first
// 			0, 5, 10, 15, 20, 25, 30
// 			1, 6, 11, 16, 21, 26, 31
// 			2, 7, 12, 17, 22, 27, 32
// 			3, 8, 13, 18, 23, 28, 33
//			4, 9, 14, 19, 24, 29, 34
//
//  Date - revision : April 6th 2005 - v 1.2
//			Version 1.1 - Initial release with app note
//			Version 1.2 - Inversion mask added, IDDR2s all bought up to top level
//
//  Author :          NJS
//
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