top4_rx.v

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

//////////////////////////////////////////////////////////////////////////////
//
//  Xilinx, Inc. 2006                 www.xilinx.com
//
//  XAPP 485 - 1:7 LVDS in Spartan3E Devices
//
//////////////////////////////////////////////////////////////////////////////
//
//  File name :       top4_rx.v
//
//  Description :     Example top level module for using a 4-bit receiver in Spartan 3E
//
//  Date - revision : November 1st 2005 - v 1.3
//			Version 1.1 - Initial release with app note
//			Version 1.2 - Inversion mask added, IDDR2s all bought up to top level
//			Version 1.3 - Auto phase aligner added, see inline notes for removing 
//				      this function if its is not required
//
//  Author :          NJS
//
//  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
//              provided t.O(you "as is". Xilinx and its licensors make and you
//              receive n.O(warranties or conditions, express, implied,
//              statutory or otherwise, and Xilinx specifically disclaims any
//              implied warranties of merchantability, non-infringement,or
//              fitness for a particular purpose. Xilinx does not warrant that
//              the functions contained in these designs will meet your
//              requirements, or that the operation of these designs will be
//              uninterrupted or error free, or that defects in the Designs
//              will be corrected. Furthermore, Xilinx does not warrantor
//              make any representations regarding use or the results of the
//              use of the designs in terms of correctness, accuracy,
//              reliability, or otherwise.
//
//              LIMITATION OF LIABILITY. In n.O(event will Xilinx or its
//              licensors be liable for any loss of data, lost profits,cost
//              or procurement of substitute goods or services, or for any
//              special, incidental, consequential, or indirect damages
//              arising from the use or operation of the designs or
//              accompanying documentation, however caused and on any theory
//              of liability. This limitation will apply even if Xilinx
//              has been advised of the possibility of such damage. This
//              limitation shall apply not-withstanding the failure of the
//              essential purpose of any limited remedies herein.
//
//  Copyright