xapp_485_readme.txt

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

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**
** Xilinx, Inc. 2006                 www.xilinx.com
**
** XAPP485 - 1:7 Data Deserialization in Spartan 3E devices
**
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**
** Author :    Xilinx, Inc.
**
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Enclosed in these folders are the files needed to generate
1:7 deserialisation designs as described in the application note XAPP485.
Included are 
A. Source code in verilog and vhdl for both 4 and 5 bit receiver designs
B. Recommended pinouts in the form of ucf files for various device/package combinations
   The format of the constraints file name is NAME_XX_Y.ucf - NAME is the name of the design
                                                              XX is the position of the macro (for example : tl = top left, rb = right bottom)
                                                              Y is a, b, c etc when there is more than one file
C. Floorplan details in Microsoft PowerPoint format for the above
D. A Microsoft Excel spreadsheet that enables the calculation of system margin and timespecs
when bit rate information is inserted.

Version 1.1 - November 2006

- Pin swapping logic as in XAPP491 added
- (Optional) Auto phase alignment function added
- Tested with release 8.2.03 of the Xilinx toolset

Version 1.0 - March 2006

- initial release, tested with release 8.1.02 of the Xilinx toolset