serdes_4b_1to7.vhd

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

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--  Xilinx, Inc. 2006                 www.xilinx.com
--
--  XAPP 485 - 7:1 LVDS in Spartan3E Devices
--
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--
--  File name :       serdes_4b_1to7.vhd
--
--  Description :     4-bit generic 7:1 serdes receiver macro for Spartan 3E
-- 			Takes in 4 bits DDR and deserialises this to 28 bits
-- 			relies very heavily on component instantiation to allow RLOCing in the code
--
-- 			data is received LSBs first
-- 			0, 4,  8, 12, 16, 20, 24
-- 			1, 5,  9, 13, 17, 21, 25
-- 			2, 6, 10, 14, 18, 22, 26
-- 			3, 7, 11, 15, 19, 23, 27
--
--  Date - revision : April 6th 2005 - v 1.2
--			Version 1.1 - Initial release with app note
--			Version 1.2 - Inversion mask added, IDDR2s all bought up to top level
--
--  Author :          NJS
--
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